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Reading Reset Manager's status register in U-Boot for POR returns 0x0 (for Cyclone5 SOCFPGA) by MAhme25 Beginner in FPGA, SoC, And CPLD Boards And Kits 01-30-2024 0 8	0	8
How do I make the u-boot semi-hosted on IntelFPGA Cyclone5SoC development kit? by ABenj2 Beginner in FPGA, SoC, And CPLD Boards And Kits 08-03-2020 0 6	0	6
What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus? by JBayl Beginner in FPGA Intellectual Property 07-22-2020 0 16	0	16
My LED is not blinking - My first NIOS II software tutorial - EP4CE6E22C8N by psouz7 Beginner in Nios® V/II Embedded Design Suite (EDS) 06-12-2020 0 3	0	3
Reducing initiation interval, relaxing loop-carried dependency by SChun19 Beginner in Intel® High Level Design 05-11-2020 0 15	0	15
Can't communicate MT25Q flash over Serial Flash Controller II Intel FPGA IP with quartus_pgm --nios2 or Nios Flash Programmer-- Error 18927 FAILED when using quartus_pgm by RPind1 Beginner in Nios® V/II Embedded Design Suite (EDS) 05-06-2020 0 4	0	4
FIR II Coefficient Read from Cyclone V HPS Freezing. by CCase1 Beginner in FPGA Intellectual Property 04-22-2020 0 9	0	9
Intel HLS (19.3) - Bad implementation of memory. by Pan Beginner in Intel® High Level Design 03-06-2020 0 7	0	7
What does Performance saturation mean when we Increase SIMD size? by MAsla5 Beginner in Application Acceleration With FPGAs 02-20-2020 0 10	0	10
How do I get u-boot-with-spl.sfp to read u-boot.scr instead of extlinux.conf? by JMurr12 Novice in Intel® SoC FPGA Embedded Development Suite 01-21-2020 0 3	0	3
Shift register implementation by ADua0 Beginner in Application Acceleration With FPGAs 01-09-2020 0 1	0	1
OpenCL host code getting compile error: ‘clCreatePipe’ was not declared in this scope by okramer New Contributor I in Intel® High Level Design 12-20-2019 0 2	0	2
report shows no DSP usage for OpenCL kernel by amrmesh Beginner in Intel® High Level Design 12-15-2019 0 10	0	10
A10 AVMM DMA has only a single MSI to Host, how to distinguish this DMA completion is from READ DMA controller, or from WRITE DMA controller? by JET60200 New Contributor I in Programmable Devices 12-07-2019 0 7	0	7
What is the X552 support for 1000baseT, SFP RJ45 transceiver? I could recognize an interface but no link gets up. It seems the ixgbe X552 driver only supports SX and LX,both having LC connector, and not 1000baseT, SFP RJ45 transceiver. by AWell15 Beginner in Ethernet Products 12-03-2019 0 8	0	8
How can I set adaptive-rx/tx in Linux? by VDiPa Beginner in Ethernet Products 11-15-2019 0 10	0	10
Why doesn't my task work when a timer is added. (with MicroC/OS-II) by RyuKucchan Beginner in Nios® V/II Embedded Design Suite (EDS) 11-06-2019 0 2	0	2
COntrol FPGA component from Linux by User1571932698773355 Novice in FPGA, SoC, And CPLD Boards And Kits 11-04-2019 0 2	0	2
Arria 10 : Uboot error by PJais1 Novice in FPGA, SoC, And CPLD Boards And Kits 11-01-2019 0 1	0	1
How to access FPGA peripherals from ARM by XChoo Beginner in FPGA, SoC, And CPLD Boards And Kits 10-16-2019 0 2	0	2
There is c code errors for using performance counter IP, but I can not debug this problem. by GKO00 Beginner in Nios® V/II Embedded Design Suite (EDS) 10-09-2019 0 1	0	1
Custom Board using Arria 10 (10AS057) with Marvell MVL88E1512 by CRubi Novice in Programmable Devices 09-02-2019 1 12	1	12
NIOS : fopen command only works if using the NIOSII Debug tool by VCham New Contributor I in FPGA Intellectual Property 07-23-2019 0 3	0	3
custom ip core by rkaib Beginner in Intel® FPGA University Program 07-19-2019 0 33	0	33
How to write to and read data from an on-chip fifo through PCIE from a computer? by SAbde7 Beginner in Application Acceleration With FPGAs 07-17-2019 0 5	0	5