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MAX10 10M04 - Not enough logic elements to use the ADC block? by James44 Novice in Programmable Devices 04-02-2024 0 9	0	9
10M16SAU169A7G ADC IO Restriction by MN23 Beginner in Programmable Devices 02-12-2024 0 3	0	3
Using multiple LVDS ADC in a single Arria 10 GX IO bank by corestar New Contributor I in Programmable Devices 11-25-2023 0 4	0	4
MAX 10 - Internal ADCs - analog inputs configuration by Amir3 New Contributor I in FPGA, SoC, And CPLD Boards And Kits 07-05-2023 0 1	0	1
MAX10 ADC DC characteristics by FrankK New Contributor I in Programmable Devices 02-01-2023 0 6	0	6
Constraints for ADC data input by KCMurphy New Contributor II in Intel® Quartus® Prime Software 10-04-2022 0 4	0	4
MAX 10 single supply LVDS max data rate by IDeyn New Contributor III in Programmable Devices 02-22-2022 0 5	0	5
MAX10 VREF minimum value by Vocabularix Novice in FPGA, SoC, And CPLD Boards And Kits 01-31-2022 0 2	0	2
FPGA models with built-in DAC and ADC? by hkkim314121 Beginner in Programmable Devices 01-30-2022 0 2	0	2
MAX10 ADC Sampling Issue after Power On by swtsven Beginner in Programmable Devices 01-29-2022 0 2	0	2
What is the internal reference voltage in MAX10 FPGAs, especially single supply. by Vocabularix Novice in Programmable Devices 12-22-2020 0 2	0	2
Sampling MAX 10 TSD using ADC Control Core running at 1 Msps by electreng Beginner in FPGA Intellectual Property 08-10-2020 1 1	1	1
Finding ADC module in Qsys in Quartus II 13.0sp1 by AGard12 Beginner in Intel® FPGA University Program 04-30-2020 0 3	0	3
MAX10 ADC TSD offset - IO bank 8 voltage? by Altera_Forum Honored Contributor II in Programmable Devices 01-09-2020 0 3	0	3
Max 10 ADC does not show as included in Project Summary Compilation by AKohl3 Beginner in Intel® Quartus® Prime Software 09-13-2019 0 3	0	3
Coniguring FPGA devices over USB by aakkü Novice in FPGA, SoC, And CPLD Boards And Kits 03-13-2019 0 8	0	8
Error with DE0-Nano ADC Controller IP by VToh Beginner in FPGA, SoC, And CPLD Boards And Kits 02-13-2019 0 2	0	2
MAX10 ADC Core Channel Sequence Issue by Altera_Forum Honored Contributor II in FPGA Intellectual Property 06-06-2018 0 8	0	8
Max 10 ADC with Nios II by Altera_Forum Honored Contributor II in Programmable Devices 06-01-2018 0 4	0	4
MAX10 Pinout - REFGND pin by Altera_Forum Honored Contributor II in Programmable Devices 05-29-2018 0 2	0	2
DE10-NANO - NIOS+ADC+DMA+ONCHIP MEMORY+HDMI on Platform Designer by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 05-04-2018 0 1	0	1
Unable to simulate MAX 10 ADC by Altera_Forum Honored Contributor II in Programmable Devices 03-27-2018 0 3	0	3
Max10: ADC not working with .pof file by Altera_Forum Honored Contributor II in Programmable Devices 02-20-2018 0 4	0	4
DE10-NANO - How to use the ADC with FPGA and NIOSII by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 01-27-2018 0 2	0	2
ADC For DE10-nano board by Altera_Forum Honored Contributor II in Intel® FPGA University Program 01-16-2018 0 0	0	0