Tag: "pll"

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	Using multiple LVDS ADC in a single Arria 10 GX IO bank by corestar New Contributor I in Programmable Devices 11-25-2023 0 4	0	4
	2 Transceivers PLL issue by gbessa Novice in Programmable Devices 05-28-2023 0 3	0	3
	Timing analysis - Timing requirements not met by germano Beginner in Intel® Quartus® Prime Software 11-14-2022 0 4	0	4
	DDR3 IP core clock by shandeep Novice in FPGA Intellectual Property 02-28-2022 0 3	0	3
	MAX 10 FPGA by klopez Novice in Programmable Devices 02-16-2022 0 5	0	5
	Very weird configuring issue by Thomas2021 Beginner in Programmable Devices 02-09-2022 0 2	0	2
	Timing constraints on PLL by Bhavana_t Beginner in Intel® High Level Design 01-18-2022 0 2	0	2
	The Jitter issue on the SDI 12G project (Quartus 20.1) by Dzmitry Beginner in Intel® Quartus® Prime Software 04-29-2021 0 2	0	2
	altera_pll Fractional-N PLL error using physical output clock parameters by HypeInst New Contributor I in Intel® Quartus® Prime Software 03-31-2021 0 3	0	3
	Cyclone V A7; PLL temperature Issue by Jan_AM Beginner in Programmable Devices 03-22-2021 0 2	0	2
	PLL frequency doubling but shouldn't by Joossss Novice in Programmable Devices 03-12-2021 0 4	0	4
	How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains by Amir21 Novice in Intel® Quartus® Prime Software 10-12-2020 0 5	0	5
	PLL Reconfiguration read of PLL registers by SDavi9 Beginner in FPGA Intellectual Property 07-28-2020 0 8	0	8
	My PLL stops working after a certain frequency (around 320 MHz) by NBody Beginner in Application Acceleration With FPGAs 05-19-2020 0 2	0	2
	Can the altera_pll version 18.0 be used on Cyclone V without the RREF_TL pin connected? by LHøi0 Beginner in FPGA Intellectual Property 04-09-2020 0 6	0	6
	The problem with two external PLL for LVDS RX by EBoln New Contributor I in Programmable Devices 01-24-2020 0 3	0	3
	PLL phase shift does not work by EBoln New Contributor I in Programmable Devices 12-02-2019 0 5	0	5
	PLL Cascade bandwidth configuration issues (fPLL) by JSwif Beginner in FPGA Intellectual Property 11-22-2019 0 1	0	1
	MAX 10 LVDS clock recovery functionality by James_Stuart Beginner in Programmable Devices 08-30-2019 0 1	0	1
	Arria 10 Device Specifications by CHebl New Contributor I in FPGA Intellectual Property 08-15-2019 0 1	0	1
	Platform designer testbench PLL component does not match entity by gyuunyuu New Contributor II in Intel® Quartus® Prime Software 08-05-2019 0 5	0	5
	ALTPLL Error: Clock Input port of PLL must be driven by non-inverted input pin or another PLL. by SMS Beginner in FPGA Intellectual Property 08-03-2019 0 9	0	9
	Problem in using 2 NIOS cores with 2 PLLs and clock sources by anaza3 Novice in Intel® Quartus® Prime Software 07-24-2019 0 8	0	8
	How to simulate an IP by 33000 Beginner in Intel® FPGA University Program 07-18-2019 0 1	0	1
	User IO pin vs PLL_CLKOUT0N pin. Can I output a clock on user IO? by JDeff Beginner in Programmable Devices 05-15-2019 0 1	0	1