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How to configure the dsp ip core to make a 16-bit 3-input adder with good timing by Jianing1 Beginner in FPGA Intellectual Property 04-01-2024 0 4	0	4
Intel High Definition DSP device with error 28 by KA_USA Beginner in Graphics 01-02-2024 0 4	0	4
DSP Builder Advanced: integrator and differentiator blocks by Altera_Forum Honored Contributor II in FPGA Intellectual Property 05-25-2023 0 1	0	1
Quartus installation not found: some functionality will not be available until you set QUARTUS_ROOTD by Sreejith_TV Beginner in FPGA Intellectual Property 05-08-2023 0 4	0	4
How to fit 2 multipliers in one DSP block - Arria V? by eran_el Novice in Programmable Devices 09-20-2022 0 7	0	7
Quartus Prime Pro Edition 27x 27 multiplier by Beng Employee in Intel® Quartus® Prime Software 12-15-2020 0 2	0	2
Is DSP Builder for Quartus 20.1+ std (Cyc V) dead or will it come back in future editions? by MKlee2 New Contributor I in Items with no label 06-15-2020 0 0	0	0
Simulation of FFT IP Core in Modelsim fails, can't find "asj_fft_dualstream" by JRose37 Beginner in Intel® Quartus® Prime Software 03-12-2020 0 6	0	6
DSP Builder standard blockset not showing up in MATLAB. by TTyag Beginner in Items with no label 02-27-2020 0 1	0	1
MATLAB crashes on opening the DSP Builder model by TTyag Beginner in Items with no label 02-26-2020 0 0	0	0
Rehosting Quartus II license by TTyag Beginner in Items with no label 02-25-2020 0 0	0	0
Hi! What are the toolboxes required in MATLAB for DSP builder? Is the "fixed point designer" a necessity for the standard blockset also? by TTyag Beginner in Items with no label 02-18-2020 0 0	0	0
how to move DSP-Builder project (or get relative output) by HEyer Beginner in Intel® Quartus® Prime Software 10-15-2019 0 4	0	4
using DSPs in the FPGA as ALMs for standard FFT IP by VenkateshSathar New Contributor I in FPGA Intellectual Property 09-30-2019 0 42	0	42
DSP builder compilation error by TMerz Beginner in Intel® High Level Design 08-13-2019 0 2	0	2
SystemConsole.designLoad does not work in MATLAB by GBies Novice in Intel® High Level Design 02-18-2019 0 2	0	2
Can a multi-channel FIR filter bank with different coefficients on each channel be realized in DSP Builder? by DHaes Beginner in Intel® Quartus® Prime Software 10-03-2018 0 1	0	1
Cyclone V DSP Cost 36x36 signed multiplication by Altera_Forum Honored Contributor II in FPGA Intellectual Property 08-03-2018 0 2	0	2
FPGA for DSP on Adaptive Dynamic Vibration Absorber by Altera_Forum Honored Contributor II in Programmable Devices 06-27-2018 0 0	0	0
DSP Builder with QuestaSim by Altera_Forum Honored Contributor II in FPGA Intellectual Property 06-06-2018 0 0	0	0
Workflow tips in Simullink by Altera_Forum Honored Contributor II in FPGA Intellectual Property 05-23-2018 1 0	1	0
Using registers to debug in SignalTap by Altera_Forum Honored Contributor II in FPGA Intellectual Property 05-18-2018 1 0	1	0
Arria 10: Packing 2 Multipliers per DSP by Altera_Forum Honored Contributor II in Programmable Devices 12-12-2017 0 2	0	2
How to force a mode onto a Stratix V DSP block? by Altera_Forum Honored Contributor II in FPGA Intellectual Property 12-01-2017 0 0	0	0
Simple MegaCore FFT Simulink Model by Altera_Forum Honored Contributor II in FPGA Intellectual Property 11-07-2017 0 0	0	0