Tag: "synthesis"

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array value miss of add by yelen Beginner in Intel® Quartus® Prime Software 03-12-2024 0 2	0	2
Quartus appears to have had a crush by yelen Beginner in Intel® Quartus® Prime Software 03-03-2024 0 5	0	5
Getting 'Timing requirements not met' as critical warning by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 12-08-2023 0 10	0	10
Timing-Driven Synthesis is skipped because it could not initialize the timing netlist by OlaG Beginner in Intel® Quartus® Prime Software 09-10-2023 0 4	0	4
Which Verilog Simulator to Install by MJ96 Beginner in Intel® FPGA Software Installation & Licensing 04-25-2023 0 4	0	4
dense packing for fourteennm_mlab_cell and not related register by matota1 Beginner in Programmable Devices 09-05-2022 1 4	1	4
Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design by CADAMS Novice in Intel® Quartus® Prime Software 03-16-2022 0 8	0	8
Is Agilex Synthesis is Timing Driven ? by dmanikanth Novice in Intel® Quartus® Prime Software 01-23-2022 0 1	0	1
Bug report: Quartus Pro version 20.3/20.4 synthesis crashes on VHDL recursive function calls with... by roeekalinsky Valued Contributor I in Intel® Quartus® Prime Software 11-11-2021 0 16	0	16
Manual simulation of a HLS design failed by ettjaakko Beginner in Intel® High Level Design 08-24-2021 0 3	0	3
Clock synthesis and de-skewing using an IOPLL in Arria 10 by roeekalinsky Valued Contributor I in Programmable Devices 08-24-2021 0 17	0	17
Total register & logic consumed from Arria 10 PAC by E-Hong New Contributor I in Application Acceleration With FPGAs 07-24-2021 0 2	0	2
Difference between Standard and Pro editions of HLS by ettjaakko Beginner in Intel® High Level Design 05-23-2021 0 1	0	1
Compiling IPs with the files of /synthesis folder by DYaro1 Novice in Intel® Quartus® Prime Software 03-11-2021 0 0	0	0
Incremental synthesis after a small constraint change? by RZhen11 New Contributor I in Intel® Quartus® Prime Software 07-19-2020 0 1	0	1
Tri0 and Pulldown synthesizable in CPLDs (MAX V, MAX II, MAX7000) by CHess4 Beginner in Intel® Quartus® Prime Software 03-13-2020 0 2	0	2
FFT IP of quartus taking resources differently in different project for same ip configuration by VenkateshSathar New Contributor I in FPGA Intellectual Property 08-30-2019 0 2	0	2
Error VPR20KMAIN using quartus commandline by EvanR Beginner in Intel® Quartus® Prime Software 03-13-2019 0 1	0	1
SystemVerilog structure or struct assignment by keyword. by Branden_Allen Beginner in Intel® Quartus® Prime Software 11-07-2018 0 1	0	1
Is the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented? by Branden_Allen Beginner in Intel® Quartus® Prime Software 11-02-2018 0 5	0	5
Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction. by MoZdk New Contributor I in Intel® Quartus® Prime Software 10-25-2018 0 5	0	5
Verilog if statement with a signed signal by AndyN New Contributor I in Intel® Quartus® Prime Software 10-02-2018 0 7	0	7
8 MHz clock from 100 MHz by Altera_Forum Honored Contributor II in Programmable Devices 08-08-2018 0 6	0	6
project compilation is taking forever to finish by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 10-09-2017 0 3	0	3
OpenCL project compilation is taking forever to finish by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 10-09-2017 0 0	0	0