N6000-PL MAX10 Build

[Beginner_in_FPGA]

Hi,

I am currently building the N6000 MAX10 BMC provided in this guide, when running the script as mentioned in the guide "./build.sh" the script throws errors. I am not able to clear this error and the file is not present in the directory. Any ideas as what to do next is deeply appreciated?

Thank you,
Best Regards.

[khtan]

Hi ,

Thanks for contacting Intel Forum. I'm Kian and will be looking into this case.

First of all, thanks for the log file. I noticed that you don't have elf2hex installed

https://github.com/sifive/elf2hex?tab=readme-ov-file

installation instructions are located in the github.

I also noticed there is a lot of file not found which is concerning thus I will setup on my side Ubuntu to test out the build as well to see what's wrong with it. 

I will get back to you once I found anything.

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hi @khtan,

I hadn't noticed that it required Standard version, I was trying to synthesize using Pro version. After doing this change I am able to go further in the script but still the build fails because the file "bmc_fw_user_retail.elf" is missing.

I can't seem to figure out what's the exact issue with the script. Attached below is the log file of the latest running. Any ideas as what to do next would be very helpful.

Thank you,

Best Regards.

[Beginner_in_FPGA]

Hi @khtan,

The above issue was just a license server issue, which was sorted out quickly.

But now the Script is stuck at another point, I have attached the log file below. If you have any idea as to what might be the cause of the same please do let me know.

Thank you,
Best Regards.

[Beginner_in_FPGA]

Hi @khtan,

Resolved the issue with .elf files not being able to be converted into .hex.

Now the sre_cat is not able to concatenate dev_img_info.hex and max10_onchip_flash.hex to output ufm_onchip_flash.hex. It is giving this warning message -

srec_cat: mem_init/max10_onchip_flash.hex: 2: multiple 0x00000000 values
(previous = 0x27, this one = 0x00)
srec_cat: mem_init/max10_onchip_flash.hex: 2: multiple 0x00000000 values
(previous = 0x28, this one = 0x00)

Any ideas to resolve this are greatly welcomed.

Thank you,
Best Regards.

[khtan]

Hi,

Sorry for the late response, I was attempting to build the BMC and also got the same error as yours.

May I know what version of BMC you're building , the github branch ( mine is max10_bmc_v3_14_0) . Wondering whether is there any error on this branch as there is newer branch in github.

I will also check whether is there any case log in the system for BMC generation.

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hi @khtan,

I am currently building the max10_bmc_v3_15_0. I will try with the max10_bmc_v3_14_0 right now, since you already got the same error as mine.

For the sre_cat there is a simple workaround by using the flag "-multiple" but I don't think it solves the issue since it basically writes two different values to the same address. This could change the Boot loader. When building using the "-multiple" it shows this critical warning and I don't know how this would affect the boot loader if the values would be truncated -

line 10980 - Critical Warning (18093): Memory depth (1048576) in the Memory Initialization File "../../../fw/max10/max10_bootloader/design/bmc_bootloader/mem_init/ufm_onchip_flash.hex" is larger than the flash memory depth (65536). Truncated remaining initial content value to fit flash memory. If you do not want the remaining initial content value to be truncated, make sure the Memory Initialization File contains the same memory depth values for the flash memory.

The cause for these might be the below mentioned critical warning since ufm_onchip_flash.hex is a cat of max10_onchip_flash.hexThere is a critical warning with the max10_onchip_flash.hex-

line 3686 - Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /home/admin/otc/ofs-bmc/rtl/max10/build/max10_onchip_flash.hex -- setting all initial values to 0

Any ideas as to how to resolve these issues would be deeply appreciated.

Thank you,
Best Regards.

[khtan]

Hi,

I tried version max10_bmc_v3_14_0 and  max10_bmc_v3_15_0 today , seems I'm getting different error on v15, passes ufm_onchip_flash.hex error  but fail at another place which is strange, rerunning the build again to confirm. Anyway looks like didn't have any issues reported in the system for BMC generation that I could pull from out.

For the srec_cat question, I will have to revert to the development team that does the ofs-bmc for this issue , tried different approaches to try resolve it but didnt seems to work or having the same warnings as yours. 

Thanks

Regards

Kian

[khtan]

Hi , 

Just an update rebuilding on max10_bmc_v3_15_0 also fails on the same location.  

Thanks

Regards

Kian

[khtan · Accepted solution]

Hi,

I had a discussion with one of our OFS-BMC team on the build issue and the srec_cat command and they are aware of the issue and due to release a new build script enhancement to resolve it. 

Issue cause : new Quartus version added additional padding zeroes in .hex file compared to the older versions.

As the new build script is undergoing corporate release process, we could try this first by manually changing the ./build.sh script first to solve the padding issue on the hex file.

Change the command from this :

elf2hex -v bmc_bootloader.elf 0x00000000 0x0001ffff --width=32 --record=4 --little-endian-mem --no-zero-fill --create-lanes=0 bmc_bootloader.hex

To this in build.sh:

elf2hex -v bmc_bootloader.elf 0x00000000 0x0001ffff --width=8 --little-endian-mem --no-zero-fill --create-lanes=0 mem_init/max10_onchip_flash.hex

I haven't confirmed on the fix yet as I'm still currently building it on BMC v14 although they mentioned the new script is targeted for BMC v15 (max10_bmc_v3_15_0). Will let you know the result later as it will take take some time to build

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hey @khtan,

It cleared the screc_cat issues, but there are still a lot more critical warnings with the build. Also not to mention the Timing Constraints are not met.
The build is completed after this but when programming the board with the binaries generated from the build and then running the tcl script as given in the guide. The 2nd tcl script - max10_syscon_flash fails stating -

Apr 04, 2024 7:18:35 PM com.altera.debug.core
SEVERE: master_read_32: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset

error: master_read_32: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset
while executing
"master_read_32 $mp $flash_cmd_read_data_0 1"
(procedure "read_memory_id" line 5)
invoked from within
"read_memory_id"
(procedure "detect_flash_vendor" line 4)
invoked from within
"detect_flash_vendor"
(file "max10_syscon_flash.tcl" line 814)
invoked from within
"source max10_syscon_flash.tcl"

Any ideas as to resolve this would be deeply appreciated.

Thank you,
Best Regards.

[Beginner_in_FPGA]

Hi @khtan,

Thank you for looking into this matter.
Will try to build with this change and let you know if it works out.

Thank you,
Best Regards.

[khtan]

Hi,

I'm checking with OFS BMC team on those critical warnings for the build BMC V3.15 as I also observed similar warnings on my end based on V3.14 and the issue you encountered running the TCL script

Thanks

Regards

Kian

[khtan]

Hi,

Could you provide the commands (& arguments) that you use for programming using flash tools? I noticed in your TCL screenshot, the directory for Quartus looks like Quartus Pro 23.1 ? or just 23.1std?

OFS team will also try on their end to replicate the scenario as well and also check the critical warnings especially on the timing failure.

For those critical warnings on pin assignments too close , it is fine to disregard the warnings as those pin assignments are board dependent. 

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hi @khtan

I was actually using the GUI mode. Now that I used the commands I think I successfully got the board programmed with the binaries since both the status and alarms LEDs are lighting green on a warm bootup.

But anyways below is the attached terminal windows of the programming of the board.

I am yet to test it out with the OPAE software and check with fpgainfo and other commands but on lspci it shows up the below attached terminal window.

If you notice in the Terminal even the E810 Ethernet Controller is yet to be programmed, once that is done I'll be checking with the OPAE software.

Thank you,
Best Regards

[khtan]

Hi ,

Good to hear that , I will check with the OFS team on the GUI programming vs command line flash tool. Did you manage to program the rest and check with the OPAE software?

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hi @khtan,

No I haven't yet started programming the board with E810 image yet, as I was caught up with some other work. Will test it out with that and update you on the same. The only thing that is remaining to be resolved is the Timing Violations, since the BMC team is already working on that, the case can be closed.

Thank you, 
Best Regards.

[Beginner_in_FPGA]

Hi @khtan

When testing with the card, did you enable PCIe Bifurcation?

Since I was building the N6000-PL , I used a server with PCIe gen4 x16, this server doesn't have support for PCIe Bifurcation. And hence I don't know whether the E810 Ethernet Controller is already programmed or not since it is not being shown in the terminal when using "lspci".

Is there any other method, using which I can confirm if my E810 Controller is already programmed, because obtaining a server with Bifurcation support may take some time. Can OPAE be used to check the same?

Thank you,
Best Regards.

[khtan]

Hi 

Sorry for the delay, for the timing violation (Critical Warning (332148): Timing requirements not met) in the build log, I've confirmed with the BMC team that it will not affect the functionality as previously they already tested the generated BMC binaries with these timing critical warnings as well.

Further investigation by the developer reveals that there is no critical timing warning issues when generated via GUI instead of command line build script.  As the warning is only comes in one seed, that warning can be ignored that as other seeds(sections) are compiled properly and the build script only takes seeds where there is no critical warnings. 

As for the checking whether the E810 controller working, was discussing with my colleague here and looks like the only way is via the pcie /lspci . I checked the OPAE commands and looks like cant check via commands  (list of commands in OPAE https://ofs.github.io/ofs-2024.1-1/sw/fpga_tools/fpgainfo/fpgainfo/)

I'm running on server with PCIE bifurcation enabled by default

Thanks

Regards

Kian

[khtan]

Hi,

Is there anything else that you want to clarify related to this case, otherwise I would like to close the case and transition this thread to community support.

Thanks

Regards

Kian

[Beginner_in_FPGA]

Hi @khtan ,

Sorry for the delayed response, looks like I'll be needing to upgrade my server to check for the E810 since my current server doesn't support PCIe Bifurcation. And hence the E810 doesn't get detected in the lanconf tool.
All my queries have been answered and you can close this case.

Thank you,
Best Regards.