Cyclone IV GX with LVDS Transceiver and Nios II

Altera_Forum · ‎09-28-2011

Hello,

i have a little problem to implement a lvds transceiver interface to my Cyclone IV GX design.

The Transceiver interfaces are directly connectet to the FPGA, you can see this on the screenshot.

And my idea was, that i connect on the LVDS pin a ALTLVDS_rx or ALTLVDS_tx block to serialize or deserialz the data what i want to send.

and my problem is jet, how can i make i rx_inclk, tx_inclk or txsyncclk ? I have no external clock for this.

my Board is the DB4CGX15 from Devboards:

Thanks....

if you have any questions, about my problem pleas tell me this...

Altera_Forum · ‎09-28-2011

Hi,

I have a second problem with the Cyclone IV GX Transceiver I Use the Quartus 11.0Sp1 Software and i have the same Error Message:

error: I/O bank QL0 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank

info: Can't select VCCIO 1.5V for I/O bank due to 1 input or bidirectional pins

info: Input or bidirectional pin rx_datain[0] uses I/O standard LVDS

have any one a solution?