DDR2 controller: error msg for bi-directional clock.

[Altera_Forum]

Hi,  

 I'm getting the following error when trying to fit a full-rate DDR2 controller to my Stratix III device.  "Error: Bidirectional pins mem_clk[0] and mem_clk_n[0] with pseudo-differential I/O standard must either use differential input path or have the output buffer's OE set to VCC along with proper ACF."   The signals mem_clk[0] and mem_clk_n[0] are definitely connected to DIFFIO_RX pins. Also I only encounter this error with the full-rate controller -- with the half-rate controller it never came up. I'm using Quartus 8.0.   Has anyone seen this before?   Thanks,   Andrew

[Altera_Forum]

Two things: 

 1 - Make sure you've made the clk pins "inout" or "bidir" on your top level design file.  2 - Make sure you're adhering to table 8-3 in the user's guide: http://www.altera.com/literature/hb/stx3/stx3_siii51008.pdf  Jake

[Altera_Forum]

Hi,  

 I'm still getting the same error message. I find that the ddr2 controller works as a half-rate but not as a full-rate. What would be different about the two with respect to pin assignments?  Are there any assignments that I should add to the assignment editor which are not needed for a half-rate?   Is there a tutorial for a full-rate controller? I was only able to find them for half-rate ones.   I'm using the Terasic DE3 board, is there an issue with using full-rate controllers on this board?  Thanks.