Debugging PCIe DMA transfer example design

[Sijith]

Hi,

I would like to have your continued support on this thread.  Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1579247#M28763

Thank you.

[VenTingT]

Hi @Sijith,

I am sorry that the previous thread got closed, as it is not advisable to leave a forum thread idle.

Could you please provide an update and post your question here based on your current debugging stage or findings?

I look forward to hearing from you shortly.

Thanks.

Best Regards,

VenTingT

[Sijith]

Thank you Ven Ting,

I really would like to have your  support to complete this project successfully. 

1)In the sub-design (Counter_FIFO_SignalTap.zip), I have been setting avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1 using the button in the FPGA board.

2)"Can you the add clock signal that drives the source_data and fifo_o_out_readdata, and the signals that carry the data before passing it to the fifo_o_out_readdata signal in the Signal Tap to check that the correct data are passed to fifo_o_out_readdata?" 

You mean I have to add th clock signal that drives the source_data and fifo_o_out_readdatain the SignalTap GUI window to view it? Then The signalTap should run in some different clock? I mean the default clock? (currently signal tap is running in the same clock as clock signal that drives the source_data and fifo_o_out_readdata .

3) "did you compile successfully on the original PCIe DMA transfer example design without adding Signal Tap?"

Yes I did

4)"There is a similar issue discussed in the Intel Community Forum."

In the thread you mentioned basically talks about compilation problem related to adding an IP to a design (so he can change it easily). Unfortunately I could not reach to a conclusion from that thread.  But in this case I gets error when I add signal tap instance and at nodes that where the design connects to DDR4 pins (I believe I did it correctly), the error "Error(17046): Illegal connection found on I/O output buffer primitive u0|emif_ddr4_b|emif_ddr4_b|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b|cal_oct.obuf to DDR4B_A[1]. The IO output buffer should only drive out to a top-level pin" happens when try to signal Tap at the node `DDR4B_A[1]`. I dont know why it is illegal to do so in this case?
(Screenshot of selected nodes are attached) FYI: My intention was to see the data flow (that created in the data generator and then streaming through avlonFIFO) to the DDR4

Regards,

Siji

[VenTingT]

Hi @Sijith,

You mean I have to add th clock signal that drives the source_data and fifo_o_out_readdatain the SignalTap GUI window to view it? Then The signalTap should run in some different clock? I mean the default clock? (currently signal tap is running in the same clock as clock signal that drives the source_data and fifo_o_out_readdata .

>> Yes, please add the clock signal that drives the source_data and fifo_o_out_readdata in the SignalTap so that we can view the clock signal in the SignalTap GUI window. Also, add the signals that carry the data before the data is passed to the fifo_o_out_readdata signal from source_data to check if the correct data is passed from the source to FIFO. 

But in this case I gets error when I add signal tap instance and at nodes that where the design connects to DDR4 pins (I believe I did it correctly), the error "Error(17046): Illegal connection found on I/O output buffer primitive u0|emif_ddr4_b|emif_ddr4_b|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b|cal_oct.obuf to DDR4B_A[1]. The IO output buffer should only drive out to a top-level pin" happens when try to signal Tap at the node `DDR4B_A[1]`. I dont know why it is illegal to do so in this case?

(Screenshot of selected nodes are attached) FYI: My intention was to see the data flow (that created in the data generator and then streaming through avlonFIFO) to the DDR4

>> Can you please attach the original PCIe DMA transfer example design (without any modification) that you mentioned and include the steps to replicate the error for me to replicate the error at my end to further investigate the issue? Please let me know if you want to send the design via email.

Thanks.

Best Regards,

VenTingT

[VenTingT]

Hi @Sijith,

Do you have any updates regarding my previous reply?

Based on the Capture_nodes_screenshot.png you attached, the signals you added in the SignalTap look like address signals. Can you please try removing these signals and instead adding the signals of ctrl_amm_0 or Avalon Memory Mapped Slave signals?

Attaching screenshot of ctrl_amm_0 signal:

(If you are unable to view the image, please right-click on the image and click 'Open image in new tab')

Please let me know if the error goes away after making these changes.

Thanks.

Best Regards,

VenTingT

[VenTingT]

Hi @Sijith,

Please let me know if there are any updates regarding the case that require my support. Otherwise, I will need to transition this thread to community support.

Thank you for your understanding.

Best Regards,

VenTingT

[Sijith]

Hi Ven Ting,

I am sorry for a bit the delay in response currently I am traveling for a conference. currently, I  have limited access to the system now. Will be able to address your questions well in two days.

Just for a clarification,

Can you please attach the original PCIe DMA transfer example design (without any modification) that you mentioned and include the steps to replicate the error for me to replicate the error at my end to further investigate the issue? Please let me know if you want to send the design via email

May I know if you were asking for the design which I gives error when I add signal Tap and compile (Actually this is a design with DMA example design with FIFO and counter), --if this is the case I were using the design I shared you in google drive

or you needed the PCIe DMA transfer example design (the original design without any modification). 

Thank you very much. 

Regards

Sijith

[VenTingT]

Hi @Sijith,

Thank you for your reply.

Since you mentioned that the design that gives error after adding the Signal Tap is the "original PCIE DMA transfer example design (without any modification)" in (2.) in the email from the previous forum thread, therefore I kindly requested that you attach the design (including the Signal Tap) for me to duplicate it at my end.

However, given your clarification that the design which gives error after adding the Signal Tap is actually the design with DMA example design with FIFO and counter, could you please attach the stp file? With that, I can add the stp to the design ( PCIE_DDR4_mod.zip) and reproduce the error for further investigation.

In the meantime, could you please also try the suggestion from my previous reply?

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

Sorry for the confusion regarding the compilation error while adding Signal Tap. It is the modified DMA transfer example design that gives error while adding Signal Tap. I am attaching the stp1.stp file that on attaching with DMA example design gives the compilation error.

Unfortunately right clicking the screenshot and clicking 'Open image in new tab' you attached goes to a Intel sign in page (see image Azure.png). It would be great if you could e-mail me the image.

Regards

Sijith

[Sijith]

Hi Ven Ting,

I would like to check if you could recreate the error I am seeing.

Also I could see the compilation errors go away when I add nodes to the signals (from the screenshot you send... also see the screenshot `Capture_nodes_suggested.PNG) attached ) you suggested to my stp file. May I know why you suggested ctrl_amm_0 to add? Is it just for testing the compilation error I am seeing? Also, I am curious is it illegal to add nodes at address signals ?

Also in signalTap GUI, some nodes (eg: signals of ctrl_amm_0 ) looks unassigned. (picture attached) is it something normal?

Also do you have any suggestion on which nodes I can add to the stp file to visualize the data flow through my modified design (to test if the data generator created data goes to the DDR4 memory element correctly and then I can read that through PCIe DMA transfer from a host computer?). As a first step, I would like to visualize the data from data generator to DDR4, Any suggestion from your end to choose the signals to add nodes?

Regards

Sijith

[VenTingT]

Hi @Sijith,

Thanks for attaching the screenshots.

I was able to replicate the error after adding the stp to the design. I believe the error is due to the incorrect nodes added to the stp.

The 'ctrl_amm_0' suggested is an Avalon Memory Mapped Slave. User can capture its signals using Signal Tap. Additionally, its signal nodes are in the signals watching list to monitor using the Signal Tap Analyzer.

For reference, you may check out the signals recommended to monitor in EMIF with the Signal Tap Analyzer in Section 14.4.1 of EMIF Arria 10 FPGA IP User Guide. My apology as EMIF IP is not my area of expertise. Should you have additional questions regarding the EMIF IP, kindly initiate a new forum post for specialized assistance.

Regarding the Capture_stp_send.png, yes, it is normal when you see some of the nodes found to be 'unassigned'. The nodes that were assigned with a specific pin location means they are input/output in the top-level module, and you had assigned them with a specific pin location in the Pin Planner (Assignments > Pin Planner). Alternatively, you may open the .qsf to view the pin assignments.

External Memory Interfaces Arria® 10 FPGA IP User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/signals-to-monitor-with-the-ii-logic.html

You may try to add the Avalon Streaming Source and Sink, and Avalon MM Master and Slave signals that from the IPs that you are targeting to the stp.

Thanks.

Best Regards,

VenTingT

[Sijith]

Thank you Ven ting.

I was trying to create a signal tap instance with nodes at signals *avalon_streaming source data* (data from data generator to FIFO and related valid and ready signals), *fifo_read_outdata* (data out from the FIFO to the emif interface DDR4) and signals of ctrl_amm_0. But somehow the data wave form is not getting in the Signal Tap GUI Data tab. The clock I used to drive the signal tap is the clock to the datagenerator (CLKUSER_100). Anything I am missing? Also great if you could re-creat it to see anything missing? I am attaching the stp file and a screenshot and a video

I believe the data from FIFO goes to the EMIF through  signals of ctrl_amm_0. But I could not locate the data signal (some number of  bit width ) in ctrl_amm_0. It would be great if you could point me that.

Also, it would be great if you could look into the modified DMA transfer design file that once I sent to you (through google drive) and verify the connection I made in platform designer is reasonable (for sending the data from FIFO to the DDR4 memory element and then reading that data from host computer through DMA transfer through PCIe)