DisplayPort TX IP Core Link Training Abort

[spte]

Hi All,

we are using the Intel DisplayPort TX IP core on Cyclone 10 GX FPGA and we see link training failures with a certain sink (monitor) of our customer.

Using a DP aux channel analyzer, we see that during the test of voltage levels and pre-emphasis, the DP TX core aborts the link training process instantly after about 60 ms.

This is caused due to a delay behavior of the sink: 

Each time, after the DP TX core writes training pattern sets (0x102) or training lane sets (0x103), the sink answers the next 8 source status reads each with AUX_DEFER, until finally providing the requested status. This results in a long duration of the whole link training process, which is aborted by the DP TX core after about 60 ms.

Tests of the monitor at a commercial GPUs shows that the link training process takes more than a second until finally succeeds.

We have no link training problems with other commercial monitors.

Questions:

• Why does the link training process not complete?
• We expect that there is some kind of  internal timeout within the DP TX core and ask of how we can change this value.
• We knew that within the sink (monitor) works a Xilinx DP RX IP core, so probably there are pre-known incompatibilities between Intel and Xilinx DisplayPort cores?

Note:

We use dp tx core version v20.0.1, config without support for DP 1.4

We use quartus pro version 22.3

I attached two aux channel analyzer logs, where the AUX-DEFER packets and the DP TX abort can be seen. I had to compress them to zip due to the forum upload restrictions.

Thank you in advance!

Stefan

[vgs]

Hello,

1) The Intel DPTX stopped the link training after failing the clock recovery phase. I may be wrong but I believe this may be because it reached a maximum number of attempts rather than a specific timeout. Per DP specs, I think a TX may give up on clock recovery after 10 failed attempts or after 5 attempts if the RX does not update values in the adjust request registers (voltage and preemphasis).

2) Apparently, the GPU DPTx gives the monitor a fair amount of time (15ms) between the write to voltage swing and preemphasis (h00103+) and checking the lane status (h00202+). The Intel DPTx  checks this after 200us. This may explain the difference but this is already more than what is mandated in the DP standards (100us). I haven't found a way to tweak this.

3) The Xilinx DP RX also took a while and multiple attempts/adjustments to establish CR with the GPU DPTx. Do you have a shorter/better DP cable available to give this a second try?

Kind regards,

Vgs

[ZH_Intel]

Hi there,

Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel