F-Tile Reference and System PLL Clocks IP

[Matt_P]

Hello FPGA Forum,

I'm working with the IP "F-Tile Reference and System PLL Clocks Intel FPGA" IP and the 'Multi Channel DMA for PCI Express' example design. I'm trying to understand the connection between the 'Refclk source' and the physical pin the clock is routed to. How is this determined or where can I understand more about this connection?

Thank you,

[VenTingT]

Hi @Matt_P,

Thanks for reaching out to the Intel Community Forum.

You may refer to the user guide below to learn more about the implementing of the F-Tile Reference and System PLL Clocks Intel® FPGA IP:

https://www.intel.com/content/www/us/en/docs/programmable/683872/23-4-4-7-0/implementing-the-76863.html

You may check out the refclk of MCDMA IP for PCIe in the Section 4.2 Clocks of the user guide below:

https://www.intel.com/content/www/us/en/docs/programmable/683821/23-3/clocks.html

Thanks.

Best Regards,

VenTing_Intel

[VenTingT]

Hi @Matt_P,

May I know if you have further questions on this case?

Thanks.

Best Regards,

VenTing_Intel

[Matt_P]

Hi @VenTingT ,

Thanks for your reply. I've been searching through the documents provided and haven't yet cleared up my understanding.

I'm trying to understand if there's a pattern to something like the following example- 
If I have a design with the 'refclk source' designated as 'refclk #3', I would expect the clock to drive the channel 3 reference pin in the F-tile, but it instead routes to the channel 2 reference pin.
Is the naming of 'refclk #3' arbitrary? Can it be renamed to 'refclk #2' to reduce confusion or mistakes?

Thank you,

[VenTingT]

Hi @Matt_P,

Thanks for your reply.

For the Refclk source of System PLL in the F-tile Reference and System PLL Clocks IP, the naming of RefClk # is fixed. The user can choose one of the 8 RefClk from RefClk[0] to RefClk[7] as the Refclk source for the System PLL.

You may enable the desired Refclk # for FGT PMA from Refclk#0 to Refclk #9. If you want the Refclk #2 instead of Refclk#3, you may enable the Refclk#2.

Thanks.

Best Regards,

VenTing_Intel

[yanghao1]

Hi @VenTingT 

Is this mean that I can choose any one of refclk source in the F-tile Reference and System PLL Clocks IP, and then enable it for FGT PMA. Since this selection is logical, and I need to assign the input clk of PLL to physical pin in qsf? (Dont care about CDR feature.)

In this case, physical refclk pin is CH3, and I can select RefClk source #2 in IP GUI. Then I assign the refclk pin in qsf to CH3?

[Paveetirra_Srie]

Hi yanghao1,

The thread has been closed. Kindly post a new forum thread to get support from our experts.

Thanks

Regards,

Pavee

Preview

[yanghao1]

Hi @VenTingT ,

I have another question about this PLL IP.

In the pinout, FGT REFCLK PIN is differential clock input, (also dont care the 8 and 9), but PLL input port is single-ended. How can I connect the differential clock input pin to the PLL ip?

[Matt_P]

Hi VenTing,

OK, thanks, that clears things up. I believe I was overthinking this.

Thanks for your help,

[VenTingT]

Hi @Matt_P,

You're welcome. I’m glad that your question has been addressed.

I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

VenTing_Intel

p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.