I cannot set 2 ffts with different input width and output width.

[masato1]

In this project, I used 2 FFT IP cores, settings is shown as below:

Length:64,Direction:Bi-directional,Data Flow:Variable Streaming,Input Order: Natural,Output Order:Natural,Representation:Fixed Point, Data Input Width: 8 bits, Twiddle Width:8 bits,Data Output Width: 15 bits

Length:64,Direction:Bi-directional,Data Flow:Variable Streaming,Input Order: Natural,Output Order:Natural,Representation:Fixed Point, Data Input Width: 14 bits, Twiddle Width:14 bits,Data Output: Width 21 bits

It can do a compilation successfully when I use Quartus Prime Standard Edition 18.1.0.

But it will give me 2 errors below when I use Quartus Prime Pro Edition 24.1.0:

Error(23415): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/intelFPGA_pro/project/sim_fft1/fft14in_altera_fft_ii_191_4jy74ay_opt_twr1.hex for ROM instance fft_reciever_inst|ifft2_inst|fft_ii_0|auk_dspip_r22sdf_top_inst|r22sdf_core_inst|gen_natural_order_core.gen_stages[1].gen_twiddles.stg_twidrom2|gen_optimized_memory_delayed.single_port_rom_component_real|new_ram_gen.new_ram_component|auto_generated|altsyncram1|ram_block2a0

Error(23415): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/intelFPGA_pro/project/sim_fft1/fft14in_altera_fft_ii_191_4jy74ay_opt_twr2.hex for ROM instance fft_reciever_inst|ifft2_inst|fft_ii_0|auk_dspip_r22sdf_top_inst|r22sdf_core_inst|gen_natural_order_core.gen_stages[2].gen_twiddles.stg_twidrom2|gen_optimized_memory_delayed.single_port_rom_component_real|new_ram_gen.new_ram_component|auto_generated|altsyncram1|ram_block2a0

[masato1]

Even I set these two fft ip cores as the same settings, it cannot pass the compilation. Is that mean there is only 1 fft IP can be set in 1 project when using Quartus Prime Pro Edition 24.1.0

[Kshitij_Intel]

Hi,

I believe you have imported your Q18.1 std project into Q24.1 pro edition.

If that's the case. Please try to create and generate the FFT IP again using Q24.1 pro edition.

Thank you,

Kshitij Goel

[masato1]

I just created a new project and generated the  FFT IP using Q24.1 pro edition.

[Kshitij_Intel]

Hi,

Even after creating new project and generating FFT IP in Q24.1 pro version, are still not able to instantiate 2FFT IP with different configurations?

Thank you,

Kshitij Goel

[masato1]

Yes,  even instantiating 2FFT IP with the same configurations cannot be complicated by Q24.1 pro verison.

[Kshitij_Intel]

Hi,

Can you try to add your FFT IP generated folder in your project and let me know.

If still issue not resolved, please share your Q24.1 project.

Thank you,

Kshitij Goel

[masato1]

I have shared my project.

if I commit the code below, it will be compilated ok.

 fft3 ifft1_inst(
.clk(clk),
.reset_n(reset_n),
.sink_valid(fft1_source_valid_s),
.sink_ready(),
.sink_error(2'b00),
.sink_sop(fft1_source_sop_s),
.sink_eop(fft1_source_eop_s),
.sink_real(real_fft1_fre[12-1:0]),
.sink_imag(imag_fft1_fre[12-1:0]),
.fftpts_in(5'd16),
.inverse(1'b1),
.source_valid(ifft1_source_valid),
.source_ready(1'b1),
.source_error(),
.source_sop(ifft1_source_sop),
.source_eop(ifft1_source_eop),
.source_real(real_ifft1_out),
.source_imag(imag_ifft1_out),
.fftpts_out()
);