Intel Agilex 5 Variable Precision DSP Blocks User Guide

[SamWinw]

Cannot find User Guide for Agilex5 Variable Precision DSP. And AI Tensor blocks in DSP.
Can only see for Agilex7 DSP UG but it is different. 

Please clarify how can get it ?

Best regards,

Sam

[Kshitij_Intel]

Hi,

Here you go 6. Variable-Precision DSP in Intel Agilex® 5 FPGAs and SoCs.

Thank you,

Kshitij Goel

[SamWinw]

K**bleep**ij,

thank you for your response but this is NOT the document I search.
It is device overview document. It only shows basic features, data types, and multipliers option.
Absolutely no implementation details, programming, configuration options

This is NOT DSP IP user guide like ones available for Stratix 10 and Agilex7.

Is normal DSP IP user guide for Agilex 5  already available ? Or not released yet ?

That's type of document what I am looking for Agilex 5:
https://www.intel.com/programmable/technical-pdfs/683037.pdf

Regards,

Sam

[Kshitij_Intel]

Hi,

This kind of documentation is not yet available but it follows the earlier Agilex family architecture with two additional features.

The Enhanced Digital Signal Processing (DSP) with AI Tensor Block within the FPGA fabric of these new Intel Agilex 5 D-Series FPGAs and SoCs inherit the design of the variable-precision DSP blocks in the earlier Intel Agilex device families, which already offer AI capabilities. In addition, it adds features derived from the tensor block used in the Intel® Stratix® 10 NX FPGAs. The Enhanced DSP with AI Tensor Block introduces two new important operations: the tensor processing capability for AI and complex number support for signal processing applications such as FFTs and complex FIR filters.

The first mode enhances AI with the INT8 tensor mode, which provides twenty INT8 multiplications within one Enhanced DSP with AI Tensor Block, and increases INT8 compute density by 5x versus earlier Intel Agilex device families. The tensor mode uses a two-column tensor structure with both INT32 and FP32 cascade and accumulation capability, and also supports a block floating exponent for improved inference accuracy and low-precision training. In addition, the AI capability of the variable precision DSP functionality has also been enhanced. The vector mode has been upgraded from four INT9 multipliers to six INT9 multipliers. These modes are extremely useful for AI-centric tensor math and for various DSP applications.

The second new mode, the complex-number operation, doubles the performances of the tensor block when performing complex-number multiplication. Previously, two DSP blocks were needed for complex-number multiplication, but this new family of Intel Agilex FPGAs and SoCs can multiply 16-bit, fixed-point, complex numbers within one Enhanced DSP with AI Tensor Block.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel