PHY Lite for Parallel Interfaces FPGA IP Arria10

[phuongnn0]

I am using an Arria10 device to implement Memocontroller use PHY Lite for Parallel Interfaces FPGA IP and get an error.
Please help me point out the error and how to fix it.

Error:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DQ_GRP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic DQ_GRP that is part of Generic Component dynamo_k025bg_dynamo_0 in region (78, 169) to (78, 180), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The DQ_GRP name(s): dynamo_0|dynamo_0|phylite_0|phylite_0|core|arch_inst|group_gen[6].u_phylite_group_tile_20|lane_gen[0].u_lane_DQ_GRP_2
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: DQ_X18 (1 location affected)
Info(175029): DQ_GRP containing T32
Info(175015): The I/O pad dynamo_0_conduit_end_reset_n is constrained to the location PIN_T35 due to: User Location Constraints (PIN_T35)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within this DQ_GRP

My assignment:

set_location_assignment PIN_T35 -to dynamo_0_conduit_end_reset_n
set_instance_assignment -name IO_STANDARD "1.5-V" -to dynamo_0_conduit_end_reset_n -entity dynamo_k025bg
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to dynamo_0_conduit_end_reset_n -entity dynamo_k025bg
set_instance_assignment -name OUTPUT_TERMINATION OFF -to dynamo_0_conduit_end_reset_n -entity dynamo_k025bg
set_instance_assignment -name SLEW_RATE "1" -to dynamo_0_conduit_end_reset_n -entity dynamo_k025bg
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to dynamo_0_conduit_end_reset_n -entity dynamo_k025bg

[AdzimZM_Intel]

Hi,

I think the location that has been set may not be available for GPIO usage.

Can you verify the available pin location for this signal in Pin Planner tool?

Which device OPN that you used for this project?

Regards,

Adzim

[phuongnn0]

Hi Adzim,

Thanks for reply.
I am a newbie.
Please be more specific.
What does Device OPN mean.
I checked in Pin Planner and confirmed location T35 is available

[phuongnn0]

Hi Adzim
My Device OPN: 10AX115S2F45I1SG

[AdzimZM_Intel]

Hi

Thank you for your feedback.

I need to know about the Bank 2K pin usage that you have configured in Pin Planner.

Can you share the pin placement from the Bank 2K and stated which IP that represent the signal?

You can your design in this forum if possible to ease the debugging process.

Regards,

Adzim

[AdzimZM_Intel]

Hi

Any feedback to my previous comment?

Regards,

Adzim

[phuongnn0]

Thanks for reply.
You can close this topic