ddr2 write/read problem

[Altera_Forum]

the control signals are came out correctly(read/write req, read/write data valid). but the read out data are not correct(compared with the witten data). I use the example_top (ddr2 hp v7.2) as the top file.  

 I really can't figure out the problem. And I want to use signaltap to observe PHY memory interface signals (mem_*), but as i added the mem_* signals to signaltap, I can't make it compiled.    is there anyway I can observe PHY memory interface signals through signaltap?   And i've saved my previous signaltap waves as vwf file, if anyone like to help me out, i would attach the vwf file here.

[Altera_Forum]

I got the same problem as you.  

I use the ALT_DQDQS as the MEMORY interface , quartus encounter a internal error when assembler process if I probe the data output from ALT_DQDQS by SignalTapII.  And I tried to use ALTMEMPHY megafunction ,but till now, it can't be simulated successfully, and it sames that the calibration process was unsuccessful.  Is any somebody can help us??Thank you very much.

[Altera_Forum]

You can't probe the DQ, DM, or DQS pins with signaltap. The best you can do is get into the datapath and look at the write and read registers just before they are latched to/from the I/O.

[Altera_Forum]

I think you misunderstand me.I don't probe DQ.DM,DQS pins with signaltapII, I probed the registers in my ddr2 controller datapath. I don't understand why this problem come up too.

[Altera_Forum]

I just don't understand why the internal error come up in assembler process. 

I guess maybe the ALT_DQDQS have some configuration to solve the problem. But I don't know how to do this configuration. I already read the ALT_DQDQS specification in detail,but it's also can't solve my problem.