Cyclone VGT Eval Board - the MAX V CPLD on board always drives flash_resetn to 1??

[Altera_Forum]

This board has a P30 flash, a Cyclone VGT FPGA and uses a MaxV CPLD to parallel load the FPGA design.  

It uses Altera's PFL loader in the Max V.   So far so good.   I'm having issues with the on board P30 Flash, and I think I see why: The MAX V CPLD initially "owns" the flash at power up,  and boots the FPGA.   One would assume that after that it would let the Cyclone V FPGA take over (in fact the example designs seem to show just that).  I managed to catch what looks like bus contention on the flash_resetn signal by using SignalTap inside the FPGA (and treating flash_resetn as a bidir pin).  I opened up the MAX V CPLD design that came with the kit and it has it's own flash_resetn signal always connected to logic 1!  This means I can NOT reset the P30 flash from the FPGA, nor can the Max V CPLD. It seems like they just rely on the power up state of the flash.. Note, I double checked, the CPLD flash_resetn output is NOT set to open drain.  The CPLD does the first step, no issues - it loads my FPGA binary and starts up the FPGA.  The problem is booting my Nios CPU after that. The flash seems to be in Identification mode, so instead of running the simple Altera copy boot loader, it tries to run the P30 id codes as a program, and of course it goes off the rails after that.   What's even more strange is that if I don't drive flash_resetn at all, it looks like it needs a pullup resistor, spiking up and down in Signaltap continuously.  The example designs from Altera (Terasic probably) all show that they make flash_resetn = cpu_resetn Which is the board level push button reset.   Anyone have experience with this board? and booting cleanly from P30 flash? So weird.