DpX4 Simulation

[Elad0708]

I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this design and it seems that the pll doesn't lock and no ref_clock or sys_clock is driven at the pll outputs. I will appricate If I can get help on this subject. 

The device is Aglilex-7. 

Best Regards,

Elad Rotem 

[Farabi]

Hello,

We will look into your PLL setting first.

1. Do you have design example we can check your PLL parameters?
2. If you reduce the output clock speed- can it lock?

possible cause PLL wont lock:

a. VCC to PLL not stable - need to capture scope shot

b. unstable refclk - need to capture scopeshot

c. PLL reset signal triggered - need to check schematic

regards,

Farabi

[Elad0708]

Hi Farabi, 

Thank you for your response. The model I have issue is simulation and not lab test. 

In simulation the pll doesn't lock or drive any clock at his outputs. 

Regards,

Elad 

[AqidAyman_Intel]

Hello,

May I know which example design that you are referring to? Can you pointed out to us?

Regards,

Aqid

[Elad0708]

DisplayPort using Agilex-7 Device. 

Elad 

[AqidAyman_Intel]

Hi Elad,

Is this from the IP simulation example itself as link below?

https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/simulation-example.html

It will be helpful if you can share the link pointing to the design that you mentioned.

Regards,

Aqid