Hierarchy not found in Modelsim during RTL simulation

[Sameer-sahu]

I am using Quartous prime 19.1 standard edition. I have a hierarchical design (comprising verilog file), see screenshot (some names hidden).

When I launch RTL Simulation from Quartus, I see that in Modelsim the same project hierarchy do not exist.

Therefore, I am not able to view the internal signals of sub modules in the wave window. How can I retain the hierarchy in modelsim to view the internal signals?

Thanks & Regards

Sameer

[SyafieqS]

Seem to me your signals are being optimized away by Modelsim.

Can you try to preserve them?

Use +acc with vopt to preserve visibility of all objects in the design or vsim -voptargs with +acc for selective design object visibility during debugging.

 Let me know any update

[SyafieqS]

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