Source Synchronous Interface Output Constraint

[Sahil_Honeywell]

Hi, 

I am trying to write timing constraints for FPGA - SDRAM communications. I know as per Intel documentation, the formulas are:

output maximum delay  = maximum trace delay for data + tSU of external register - minimum trace delay for clock

output minimum delay = minimum trace delay for data  – tH of external register - maximum trace delay for clock

Now, For my design I have the maximum & minimum trace delays from PCB design of the board (considering 16 data lines between FPGA & SDRAM. I also have the tSU from SDRAM data sheet. 

My questions are:

1) To calculate the board delay, I looked at the data (D0-D15) trace length between FPGA & SDRAM, using the PCB designer tool. Using the trace length and other parameters, I calculated the min & max board delay between FPGA and SDRAM. Is that the right way of doing it?

2)  How can I calculate the minimum & maximum trace delay for the clock? There is only (clock) line going from FPGA to SDRAM, so it will have only 1 delay value. How do I calculate min and max for the clock trace? 

Please advise

Thanks

Sahil

[IntelSupport]

1. Generally is yes. Calculating the minimum and maximum board delays between the FPGA and SDRAM based on the trace length is a good starting point and right way to do.

2. The clock's lowest and maximum trace delays can be determined similarly to how the data lines are. The lowest and maximum trace delays for the clock can be calculated using the PCB designer tool and the measured trace length of the clock line. You can also take into account additional elements like the skew between the clock and data lines, the transmission delay through any clock buffers or inverters, and any additional circuits that might impact the clock delay.

[SyafieqS]

Let me know if there is any concern on this.

[SyafieqS]

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