Adding logic types to waveforms, using Modelsim SE

[Altera_Forum]

Hi Guys, 

  I've searched through the EDA tools section on Modelsim waving, and didn't see anyone else complaining of this, please help!   I'm simulating a system verilog design, and am having trouble capturing a waveform with "logic" data types in it. My scripted vlog process successfully compiles the design using -sv, etc, and I when in Modelsim, I can see that the logic signal is present in the design when I manually search for it. I can even "add wave" the signal and manually see it, all is good.   My problem is generating a .wlf file that contains that signal. It seems the only way I can dump the simulation into a wlf file, and include that logic type is if I manually specify that exact signal.   Let me explain exactly what I have tried :  In my test bench code I have $wlfdumpvars(0,T);  From the command line, I do :  vsim -t ps -l sim.log -c work.TB -do "add wave -r /TB/iDUT/* ; run 1us ; exit"  This generates a beautiful waveform with regs and wires and busses and hierearchy, etc, but no logic signals! To get a logic signal in there I have to do :  vsim -t ps -l sim.log -c work.TB -do "add wave -r /TB/iDUT/* ; add wave sim:/TB/iDUT/freq_mode ; run 1us ; exit"  I get the same waveform, successfully capturing freq_mode which is defined an input logic type, but capture no other logic signals in the design.  I've tried :  vsim -t ps -l sim.log -c work.TB -do "add wave -r /TB/iDUT/* -logic ;run 1us ; exit"  but the logic parameter doesn't seem to do anything, might aswell have not been there.  So to summarize, i cannot get Modelsim SE to dump logic signals into my waveform without manually specifying the precise signal I am after. I want to recursively add all signals of type logic in my design using command line parameters. Ive tried looking in the modelsim ini file for any magical key words, no luck. I've tried turning on verilog compiler, no luck. For some reason Modelsim does not want to dump logic types!  HELP! :confused:   and Thanks!