Always block within always block

Altera_Forum · ‎05-03-2013

Hi guys,

Is it possible to use always@block within always block? The reason I want to do that is I try to construct multiple synchronised blocks using For loop, and you need to put loop statement in a always/initial block. My code is like:


always
begin
  for(i=0;i<5;i=i+1)begin
    always@(posedge clk)
    begin
    ...
    end
  end
end

I'm not sure whether this is synthesizable or not, please give some advice.

Cheers.

Altera_Forum · ‎05-03-2013

You'll want a generate statement

In this example: http://www.asic-world.com/verilog/verilog2k2.html

You can replace memory U with your always structure

Just be sure you don't generate multiple drivers for whatever reg you are writing

Altera_Forum · ‎07-15-2013

--- Quote Start ---

You'll want a generate statement

In this example: http://www.asic-world.com/verilog/verilog2k2.html

You can replace memory U with your always structure

Just be sure you don't generate multiple drivers for whatever reg you are writing

--- Quote End ---

Can this example be synthesized?

Altera_Forum · ‎07-15-2013

generate-for loops are synthesizable.

Altera_Forum · ‎07-16-2013

It does not make sense for an always block within an always block

yes, generate if is better choice