Avalon mm Master BFM

[Aswinkrishnan]

I have being trying to do bus simulation on my avalon slave with avalon mm master bfm.

The simulation output is wrong. For example when I write to an address c0 and write data into it, but not writing correctly in the slave. I will share a screenshot below. Do you know why the master not writing into a particular slave address. The second screenshot include a code which I am using to push a command in to the slave.

[Aswinkrishnan]

I will try your suggestion. Maybe single addressable 8-bit registers could be tested. 

Regarding the qwork example that you provided with multiple slave IP's such as on-chip RAM, when I did run the simulation, the readdatavalid is getting asserted after a clock cycle. Hence the data that is being written to RAM will be returned xxxxxxxx's when reaching the BFM master.

Therefore, what component is asserting readdatavalid and how can we remove the delay between readdata signal and readdatavalid signal?

The screenshot 1 below is the console window which reads the data that is being read.

The screenshot 2 below is the problem that I stated above regarding readdatavalid signal.

I haven't made any changes in your program except writing to ON-chip RAM instead of PIO_control.

[ShengN_Intel]

Hi,

For On-Chip RAM, have to look at the test program in qsys_system_tb_burst.sv. Include that will be able to simulate the On-Chip RAM. The address is addr = ONCHIP_RAM + 4*i; as the symbol width is 8 while the data width is 32.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Any further concern or update?

[Aswinkrishnan]

Thank you for the replies. I will look at your suggestions. No more updates.