Cyclone IV altgx simulation glitches

[shawn4]

To Whom It May Concern: 

When simulating the ALTGX transceiver Using Questa or Modelsim PE I am seeing glitches on the Tx output waveform. Is this expected? After a rising edge of the data the glitch appears as a narrow pulse 1 serial clock cycle. In the simulation the channel corresponding dout_tx0 has a constant input value.

Thanks,

Shawn

[Kshitij_Intel]

Hi,

Can you confirm that you have a local clean reference clock?

Thank you,

Kshitij Goel

[shawn4]

Hi K**bleep**ij,

 Yes, the reference clock is clean (clk98m_in shown below).

Thanks,

Shawn