I have a small .bdf file and another VHDL file instantiated inside this .bdf.
I created this bdf just to test the small VHDL file I am creating. The thing is that I test it step by step and I have an input that I want to set during simulation in Modelsim and also I do not want to assign a pin on it or drive it inside the code. I just need it floating.
While I am trying to create the VHDL file out of the bdf file I get a default value missing error.
Then I go inside the small VHDL file under test and I insert a default assignment at the port as follows:
compareAstd : in std_logic_vector(COUNTERWIDTH-1 downto 0) := (OTHERS => '0');
This default value assignment though does not get passed inside the converted-to-VHDL bdf file. So the compiler shows an error at the converted bdf file that the port input doesnt have default value.
My question is how to suppress this error or how can I let Quartus pass the default value from every VHDL file, that is represented as a symbol inside the bdf file, to the translated-to-VHDL bdf file?
Thank you
