Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Discrepancy in Register Count between Compilation Report and TCL/Timing Report

RazMo
Beginner
575 Views

Hi

I see, in multiple design we have,
a mismatch between the Compilation Report and TCL/Timing report.

for example,
In the "Compilation report" the total number of registers was 4263

In the TCL get_registers and Timing Analyzer query
total number of registers was 4482

There is a gap in the number of reported registers.

I would like to understand what is the reason for the discrepency.

This issue has become particularly significant as we are currently investigating a module that has shown a substantial increase in size between projects.
The Compilation Report showed a significant increase in the number of registers for this module between projects,
while the number of registers reported by the TCL command remained nearly the same.

We are finding it challenging to identify the root cause of this increase in module implementation due to the uncertainty introduced by the aforementioned discrepancy.

Thanks,

Moshe

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sstrell
Honored Contributor III
553 Views

You can't use get_registers from the Name Finder as a reference for resource usage.  There are internal registers of IP and hard blocks that have timing paths measured by the TA and not counted as used device resources.  As for the others 4248 + 15 I/O registers = 4263 from the flow summary.

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RazMo
Beginner
547 Views

Hi,

 

The issue is that also with tcl console get_registers command I get the same number of registers (not from STA).

To focus my issue,
using get_registers purpose was to investigate why a module utilization increased between 2 projects
for that I need to find a reliable way to list the registers 
and it needs to be in correlation to the Compilation report.

 

Thanks,

Moshe

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SyafieqS
Moderator
402 Views

 As mentioned there are internal registers of IP and hard blocks that have timing paths measured by the TA and not counted as used device resources which you have to do manually.


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SyafieqS
Moderator
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