Error 10392

[Altera_Forum]

I have the following VHDL configuration file (which I got from someone else). 

 configuration ssi_rtl_cfg of ssi is  for rtl  for all : tmr_dff  use entity sta101_lib.tmr_dff(rtl);  end for;  for all : ssi_tap_tracker  use entity sta101_lib.ssi_tap_tracker(rtl);  end for;  for all : ssi_ckd  use entity sta101_lib.ssi_ckd(rtl);  end for;  for all : ssi_struct_reg  use entity sta101_lib.ssi_struct_reg(rtl);  end for;  for all : ssi_shift_ctrl  use entity sta101_lib.ssi_shift_ctrl(rtl);  end for;  for all : ssi_shifter  use entity sta101_lib.ssi_shifter(rtl);  end for;  for all : ssi_sb_ctrl  use entity sta101_lib.ssi_sb_ctrl(rtl);  end for;  for all : ssi_ssic  use entity sta101_lib.ssi_ssic(rtl);  for rtl  for all : ssi_ptr_gen  use entity sta101_lib.ssi_ptr_gen(rtl);  end for;  for all : ssi_cnt_gen  use entity sta101_lib.ssi_cnt_gen(rtl);  end for;  end for;  end for;  end for; end ssi_rtl_cfg;  On the line highlighted in red, I get the following error.   Error (10392): VHDL Block Specification error at ssi_rtl_c.vhd(82): cannot find "rtl"   This looks like valid VHDL, and it works with the Cadence NC-VHDL compiler. It's not the best coding practice, I know, but is there some reason Quartus doesn't like it? The architecture "rtl" is supposed to refer to an architecture of the entity sta101_lib.ssi_ptr_gen. This architecture is called out in another file which is also in my project and which compiled correctly.   Is there some restriction on hierarchical configurations in Quartus?   Thanks,   John Jones

[Altera_Forum]

What I had to do to make this work was create a configuration for the rtl architecture that the compiler could not seem to find. I created it in the same design file and then I had problems with the compiler not being able to see the library. This is a VHDL error and I had to add a library and use directive just before each of the two configuration design elements. 

 After all that, it compiled and fitted.