Found a few instances of this and there has not be a solution identified.
Altera has posted that this message will occur if you're using SGMII in the TSE MAC on Cyclone IV GX. I'm using RGMII so that shouldn't be what's causing it.
Anyway here it is:
Error (176559): Can't place MPLL or GPLL PLL "test_sys_sopc:test_sys_sopc_inst|test_sys_sopc_ddr_ram:ddr_ram|test_sys_sopc_ddr_ram_controller_phy:test_sys_sopc_ddr_ram_controller_phy_inst|test_sys_sopc_ddr_ram_phy:test_sys_sopc_ddr_ram_phy_inst|test_sys_sopc_ddr_ram_phy_alt_mem_phy:test_sys_sopc_ddr_ram_phy_alt_mem_phy_inst|test_sys_sopc_ddr_ram_phy_alt_mem_phy_clk_reset:clk|test_sys_sopc_ddr_ram_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_mfl3:auto_generated|pll1" in PLL location PLL_1 because I/O cell "clock_100M" cannot be placed in I/O pin Pin_V11 (port type INCLK of the PLL)
I'm trying to port the UDP Offload example to the Cyclone IV GX development kit, and it's been pretty difficult. I'm now stuck on this hiccup.
Any help?
