FIR II IP Library in Platform Designer

[rosesea]

Hi,

Has anyone here ever used the FIR II IP library in Qsys for digital signal processing from the ADC output on the DE10-Standard FPGA board? Or are there any configuration examples for using this IP library?

I'm having trouble understanding the user guide at the following link: https://www.intel.com/content/www/us/en/docs/programmable/683208/17-1/about-the-fir-ii-ip-core.html

Thank you,

rosesea

[FvM]

I guess it's not specifically a problem of the FIR II IP user manual, it's fairly clear. Rather think you are missing a specification of the intended filter operation.

[Kshitij_Intel]

Hi,

Can you please be specific what is the issue you are facing?

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel