Get stuck at Analysis & Synthesis

Altera_Forum · ‎02-28-2011

Hello all,

I'm new with hardware description language.

I'm current design a TEA(Tiny Encryption Algorithm) using VHDL. I've finish the code, but it get stuck at Analysis & Synthesis, it just keep Analysis & Synthesis and never give any further information

Here is the code


LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TEA is
port( 
 encrypt  : in  bit;
 v0   : in  bit_vector(63 downto 0);
 v1   : in  bit_vector(63 downto 0);
 k0   : in  std_logic_vector(63 downto 0);
 k1   : in  std_logic_vector(63 downto 0);
 k2   : in  std_logic_vector(63 downto 0);
 k3   : in  std_logic_vector(63 downto 0);
 out0  : out  bit_vector(63 downto 0);
 out1  : out  bit_vector(63 downto 0)
);
end TEA;
ARCHITECTURE struct OF TEA IS
 
BEGIN
 
 
process(encrypt,v0,v1,k0,k1,k2,k3)
 
 constant delta : integer := 2654435769;
 variable m0  : std_logic_vector(63 downto 0) := to_stdlogicvector(v0);
 variable m1  : std_logic_vector(63 downto 0) := to_stdlogicvector(v1);
 variable sum  : integer := 0;
 variable temp0 : integer := 0;
 variable temp1 : integer := 0;
 
 begin
 
  temp0 := conv_integer(m0);
  temp1 := conv_integer(m1);
  
  
  if encrypt = '1' then
  
   en: for i in 0 to 63 loop
    sum  := (sum + delta);
    
    temp0 := temp0 + CONV_INTEGER( TO_STDLOGICVECTOR( to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m1) sll 4) + k0) xor to_bitvector(conv_std_logic_vector((temp1 + sum),64)) xor to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m1) srl 5) + k1) ) );
    m0  := conv_std_logic_vector(temp0,64);
    temp1 := temp1 + CONV_INTEGER( TO_STDLOGICVECTOR( to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m0) sll 4) + k2) xor to_bitvector(conv_std_logic_vector((temp0 + sum),64)) xor to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m0) srl 5) + k3) ) );
    m1  := conv_std_logic_vector(temp1,64);
    
    
   end loop en;
   
  else
  
   sum := conv_integer(TO_STDLOGICVECTOR(to_bitvector(conv_std_logic_vector(delta,64)) sll 5));
   de: for i in 0 to 63 loop
    
    temp1 := temp1 - CONV_INTEGER( TO_STDLOGICVECTOR( to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m0) sll 4) + k2) xor to_bitvector(conv_std_logic_vector((temp0 + sum),64)) xor to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m0) srl 5) + k3) ) );
    m1  := conv_std_logic_vector(temp1,64);
    temp0 := temp0 - CONV_INTEGER( TO_STDLOGICVECTOR( to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m1) sll 4) + k0) xor to_bitvector(conv_std_logic_vector((temp1 + sum),64)) xor to_bitvector(TO_STDLOGICVECTOR(to_bitvector(m1) srl 5) + k1) ) );
    m0  := conv_std_logic_vector(temp0,64);
    
    sum  := (sum - delta);
    
   end loop de;
   
  end if;
  
  out0 <= to_bitvector(CONV_STD_LOGIC_VECTOR(temp0,64));
  out1 <= to_bitvector(CONV_STD_LOGIC_VECTOR(temp1,64));
end process;
END struct;

It didn't give any error or warning when run the Analysis & Synthesis.

many thanks