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How can I generate Verilog IP in Megafunction?

Altera_Forum
Honored Contributor II
‎08-13-2014 07:33 PM
1,137 Views

Hi guys: 

I'm trying to instantiate a FIFO in Megafunction, however the file is in VHDL, how can I generate or convert it to Verilog? 

Is there any way to set the megafunction to output a Verilog file? 

Thanks in advance!! 

 

Yumeng
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Altera_Forum
Honored Contributor II
‎08-13-2014 07:35 PM
443 Views

Stupid question. Problem solved 

Sorry
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