How to get Quartus to ignore debug pins in top-level

[Altera_Forum]

I apologize if this has been posted before. I'm sure it has, but my search skills have failed to turn up the answer. I have been developing a design using Cyclone IV on a DE2 development board. I am now looking to make a production version, and the variant of the Cyclone IV that is on the DE2 board is way, way more than what I need. I would therefore like to fit the design into one of the 144-pin variants that come in more friendly packages. 

 I just today discovered the "revision" function that allows me to not have to just clone the project directory and have two sets of all the same design files, but rather one set of design files and two sets of compiler instructions. So that's good. However, my design contains certain pins at the top-level that are just there for debug (display the value of register X always on the seven segment display, and so on). I don't want to delete them from the design, because they are useful in debugging. I also don't want to route them into the 144-pin version, because that's 56 pins routed for no reason. My final board won't have any LEDs or seven-segment displays on it.  So, I would like to tell the fitter "do not route this node". In a C or C++ program, I would use# ifdef DEBUG or something like that, to guard the bits of code I don't want compiled into the final version. That's essentially what I'd like to do here.  Now, I have also today discovered something called a "virtual pin", and seen it suggested. It seems that this is an off-label use for the "virtual pin" (which seems to be intended to allow partial fitting of sub-blocks with too many I/O), but I tried it. I opened up the Assignment Editor and set all the offending pins to "Virtual". (They turned yellow.) The result has been that the seven-segment pins still appear in the pin out, but now they don't appear *at all* in the assignment editor.  Now, my questions: (1) is "virtual pin" the right way to do this, or is there some other way to tell the fitter to ignore those nodes? (I could wrap the whole top-level file in a super-top-level file, I suppose, but that would defeat the "revision" concept.) (2) If "virtual pin" is the right way, can somebody spell out, as if to a small child, how to do that? I can't make head or tail of the manual, and it seems that what I tried is not the right method.

[Altera_Forum]

A virtual pin is really for telling quartus that the IOs in your logic are not to be connected to pins, because you will probably connect something else later. Usually used for early compiles with lower level blocks before the upper levels are ready, so you get an idea of your resource usage and timing specs. I dont know how they behave with a final design. 

 Why not add a constant, or generic in your code that turns the debug on or off? You can set top level generics from within quartus.