How to see the true clock period in TimeQuest?

[Altera_Forum]

In some design, I will use the output of counter to make a clock signal if the demand for clock period is not very strict. In sdc file, I can use comand:  

 create_generated_clock divide_by   to describe the generated clock. In TimeQuest, I can use "Report Clocks" to see the different clocks I have in the design. But in Clock Summary, it lists all the clock based on description, for example, the counter is drive by a 40ns base clock and the q[1] will be 160ns in theory. But, it will not be exactly 160ns, it must has error，the ture period may be around 160ns. And I remember I can see the true clock period in my design in an option, but now I can not find it.  So anybody can help me which option I should run that I can check the true clock period in TimeQuest?  Thanks very much.

[Altera_Forum]

Why should q[1] period be not exactly 160ns? Provided the base clock is exactly 40ns, this is true. 

I think you are missing a point about what TQ is supposed to do. TQ don't calculate design clocks: period and phase of clocks are indeed inputs you feed to TQ in order it can calculate the behavior of other signals, for example their relationship with the latching clock when they get to a register. Then if you use create_generated_clock or create_clock and declare a clock period different from the real one, TQ would use this one you specify, and all analysis results will be according to this value. From what you say, I believe you intend to evaluate q[1] signal jitter. In this case you only need to specify in TQ the 40ns base clock and analyse the q[1] timing.

[Altera_Forum]

--- Quote Start ---  Why should q[1] period be not exactly 160ns? Provided the base clock is exactly 40ns, this is true. I think you are missing a point about what TQ is supposed to do. TQ don't calculate design clocks: period and phase of clocks are indeed inputs you feed to TQ in order it can calculate the behavior of other signals, for example their relationship with the latching clock when they get to a register. Then if you use create_generated_clock or create_clock and declare a clock period different from the real one, TQ would use this one you specify, and all analysis results will be according to this value. From what you say, I believe you intend to evaluate q[1] signal jitter. In this case you only need to specify in TQ the 40ns base clock and analyse the q[1] timing.  --- Quote End ---    Thanks very much. You mentioned this "Then if you use create_generated_clock or create_clock and declare a clock period different from the real one, TQ would use this one you specify, and all analysis results will be according to this value.", I think this is same as my understanding, that TQ will calculate the clock based on my description. But let me take another example, if I need use FPGA to generate a very slow clock signal for the chip which is outside the FPGA. Since the clock is very slow (e.g. period=10240ns), I use counter and drive by 40ns clock, and q[7] will be 10240ns. However, based on the theory of digital counter, there should be error between ture clock period and ideal period. If I want to check the true clock, to see whether the error is small enough for my chip, can I check it in TQ or there is no approach to do that?  Thanks very much.

[Altera_Forum]

A digital counter divides the clock *exaclty*. There's no error. 

 If you have a 40 ns clock and use counter of 256, you get a clock with 10240 ns period exactly. If you have a 40.0001 ns clock, you get a clock with 10240.0256 ns period exactly.  The input clock may and will have fluctuations that will affect the generated clock. The generated clock will also have higher jitter. But period wise, the divider has zero error.

[Altera_Forum]

--- Quote Start ---  A digital counter divides the clock *exaclty*. There's no error.  If you have a 40 ns clock and use counter of 256, you get a clock with 10240 ns period exactly. If you have a 40.0001 ns clock, you get a clock with 10240.0256 ns period exactly.  The input clock may and will have fluctuations that will affect the generated clock. The generated clock will also have higher jitter. But period wise, the divider has zero error.  --- Quote End ---    Thanks very much, it seems my original understanding about counter to create the clock signal has problem. How can I check the clock jitter in TimeQuest?  Thanks again.