Instantiating 10G BASE-R PHY IP Transceiver for Stratix V FPGA

[Altera_Forum]

Hi,  

 I am new to Quartus, verilog, and FPGAs, and am trying to learn how to create a 10G BASE-R PHY Transceiver. Here is the code I have so far; I have been following the 10G native phy provided on the altera wiki and replicating the parts I need for BASE-R:    module bit_generator (   //inputs input wire phy_mgmt_clk, input wire pll_ref_clk, input wire reset_reset, input wire reconfig_reset, input wire rx_serial_data, input wire rx_seriallpbken,   //unassigned inputs - Unsure if they go here or outside module declaration input wire xgmii_tx_clk, input wire rx_serial_data_0, input wire xgmii_tx_dc_0[71:0],     //unassigned outputs - Unsure if they go here or outside module declaration output wire xgmii_rx_clk, output wire rx_data_ready, output wire xgmii_rx_dc_0[71:0], output wire tx_serial_data_0,   //ouputs output wire errorFlag, output wire [100:0] errorCount, output wire tx_serial_data, output wire tx_ready, output wire rx_ready, output wire [63:0] prbs_data_rx_top );   //wires wire [63:0] prbs_data; wire [91:0] reconfig_from_xcvr; wire [139:0] reconfig_to_xcvr; wire phy_mgmt_clk_reset; wire pll_locked; wire pll_powerdown;     wire tx_pma_clkout; wire rx_pma_clkout;   //unknown if needed for BASE-R wire reconfig_busy; wire lock; wire rx_is_lockedtodata; wire rx_is_lockedtoref;       wire tx_cal_busy; wire rx_cal_busy;   //unknown if needed for BASE-R wire reconfig_mgmt_readdata; wire reconfig_mgmt_waitrequest;   //Reg reg [63:0] rx_data;   //Reconfig Controller xcvr_reconfig top_reconfig(  //inputs  .reconfig_from_xcvr (reconfig_from_xcvr),  .reconfig_mgmt_address (0),  .reconfig_mgmt_read (0),  .reconfig_mgmt_write (0),  .reconfig_mgmt_writedata (0),    //reconfig management  .mgmt_rst_reset (reconfig_reset),  .mgmt_clk_clk (phy_mgmt_clk),    //ouputs  .reconfig_to_xcvr (reconfig_to_xcvr),  .reconfig_busy (reconfig_busy),  .reconfig_mgmt_readdata (reconfig_mgmt_readdata),  .reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest)    );          //BASE-R Transceiver Instance  baser_xcvr1 top_baser_phy_ip_inst(  //inputs    //PLL, CDR, and Loobback  .pll_ref_clk (pll_ref_clk)m  .pll_powerdown (pll_powerdown),  .rx_set_locktodata (1'b0),//dont know if needed  .rx_set_locktoref (1'b0),//dont know if needed    .rx_serial_data (rx_serial_data),      //Transceiver Reconfiguration Interface  .reconfig_to_xcvr (reconfig_to_xcvr),    //outputs  .tx_pma_clkout (tx_pma_clkout),  .rx_pma_clkout (rx_pma_clkout),    //pll, cdr, and loopback  .pll_locked (pll_locked),  .rx_is_lockedtodata (rx_is_lockedtodata),  .rx_is_lockedtoref (rx_is_lockedtoref),    .tx_serial_data (tx_serial_data),    .tx_cal_busy (tx_cal_busy),  .rx_cal_busy (rx_cal_busy),    .reconfig_from_xcvr (reconfig_from_xcvr)    );      always @ (posedge tx_pma_clkout)        always @ (posedge rx_pma_clkout)       endmodule   I have a couple of questions and would like some input on what I am missing and what from this code can be omitted. I have some variables in the section "unassigned inputs/ouputs" that don't know whether they should be assigned in the transceiver instance or reconfiguration controller instance. Also, should they be placed inside or outside the module declaration? This confused me because some variables that the PHY IP User Guide mentions as inputs/outputs are created here as just wires. Finally, are there variables I am missing that I need to declare and assign, and is there anything that does not belong here?  Thanks in advance