Network traffic model

[Altera_Forum]

I need to design a network traffic (TCP) model with a line rate of 100Mbps. The parameters in the design requires many multiplications and divisions. I want to design in verilog but I am not very sure whether QuartusII will be able to synthesize my design (multiplication and division) or not. Can anybody give me some idea about it?

[Altera_Forum]

In the Quartus handbook, see Volume 1, Section II, Chapter 6 under "Inferring Multiplier and DSP Functions from HDL Code". 

 If you need more control than you can get with inference from RTL or need something that can't be inferred, instantiate a megafunction. There is more than one megafunction for multiplication and at least one for division.

[Altera_Forum]

Also see the "Advanced Synthesis Cookbook: A Design Guide for Stratix II and Stratix III Devices" available at http://www.altera.com/literature/lit-manual.jsp.

[Altera_Forum]

Thank you!!