Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Problem with Qsys when creating PIO

Altera_Forum
Honored Contributor II
1,217 Views

I am beginning to create a hardware with Qsys. 

The system that I want to create has 4 ports: clk(input), reset(input), a1(input), a2(output). 

I added a nios processor, a on-chip memory, a jtag uart, a pio_0, a pio_1. 

I also followed step by step as the instruction of creating the simplest nios program said. 

I set pio_0 to be input, pio_1 to be output in Basic Settings/Direction. 

However, when I generate this hardware, it only has 2 ports: clk and reset. 

I saw that 2 PIO components have external_connect but I don't know where to connect them. 

 

Would you please tell me why I can't create 4 ports?
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Altera_Forum
Honored Contributor II
473 Views

I'm sorry. I solved it.

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Altera_Forum
Honored Contributor II
473 Views

 

--- Quote Start ---  

I'm sorry. I solved it. 

--- Quote End ---  

 

Hey mate 

How did you solve it ? 

thnx
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Altera_Forum
Honored Contributor II
473 Views

Double click the 'external connection' and you should get a name you can edit. Put a suitable name here, then generate, and you will have the relevant signals as ports on the QSYS system.

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