Hi folks, I'm new to these forums and the Quartus II software
I been debugging a design that I have been given and have realized that any primitive(i tried CARRY/NOT/BUFFER) or VHDL design that I instantiate within the parent block schematic is not synthesized. That means that I cannot find the instances or nodes (the names that appear in the block schematic when I place them) in the assignment window or floor planner window.
The design compiles fine though, but I do get this warning message:
Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.
and the log shows (Mariachi is the name of the project) :
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Mariachi -c Mariachi
Do I have to edit the command line so that the synthesized design can be updated? If so where is the option? I've been looking around Assignment > Settings > Analysis & Synthesis Settings , but have not been able to identify anything that would cause this error.
I'm under the impression that the design is in some type of "locked" state, can anyone help me with this?
