Quartus 9.0sp2 compiler bug

[Altera_Forum]

I have an interesting problem, which I'm pretty sure is a bug. 

 I have been compiling for a max7128  I have a vhdl file which, apparently uses 134 macrocells, but I didn't know that at the time. When I compile for the max7128 Quartus compiles it, with no errors and reports that I'm using 103 macrocells. When I do a simulation of the file. About half of my signals stay at logic 0. I thought it was a problem with my code, during my debugging process of about 8hrs... I tried changing the device to a max2 chip it compiled fine and simulated fine.  I can know repoduce the bug, reliably, I compile for the 7128 chip no errors (103 macrocells), but my code doesnt work, I compile for a 7160 chip no errors (134 macrocells) code works fine.  Obviously my code won't currently fit on a 7128, but with some modifications I was hoping to make it fit, but its a big problem when Quartus tells me it fits, but the code doesn't work.  Any suggestions/ work arounds?  I have attached a copy of the code which reproduces the error... or lack of an error.

[Altera_Forum]

Well so far I can't find an explantion. I've compared the compilation reports for both devices and the only thing I see is that when compiling for the 7128, the following message is printed twice: Info: Promoted pin-driven signal(s) to global signal Info: Promoted clock signal driven by pin "Init" to global clock signal Info: Promoted clock signal driven by pin "CA" to global clock signal 

 whereas for the 7160 it is only printed once.  A mystery indeed. I wouldn't necessarily say the difference in macrocells is confirmation of a problem but the fact you say one works and the other doesn't is.  Jake

[Altera_Forum]

Yeah I would contact your FAE and get him looking at it. Something is amiss. 

 Looks like letting the fitter choose the device it selects the 7160.  Jake

[Altera_Forum]

I'm curious. Try this version. I've adjusted some of the compilation settings. Now the design results in 96 macrocells in both devices (by eliminating some of the auto functions). 

 Jake

[Altera_Forum]

I could verify, that Quartus produces different code with a larger device, e.g. a MAX7160S. I also could see, that SimCount registers aren't inferred in the 103 macrocell version. My first thought was, that the issue is related to the usage of unitialized variables instead of regular signals for two counters in the simulatorca process. But the behaviour with signals is identical. Thus it seems to be a bug. 

 I know, that a CPLD logic synthesis is considerably different from FPGA synthesis in Quartus (Max II is actually a small SRAM based FPGA with non-volatile configuration memory rather than a CPLD).   I could trace back the issue back to Quartus V6.0, that showed similar behaviour, while in V5.1, the simulation output was different. The macrocell consumption was still different between 7128and 7160, so I fear, that part of the design has been also removed in this version.