In a block diagram (BDF) I have instantiated a component (BSF) that has a normal port map of signals and also includes generic parameters that are VHDL generics. I want to be able to route these VHDL generic parameters on the block diagram to this component so that when I create a symbol from the BDF the generics are routed through this lump of hierarchy.
To achieve this I thought having a PARAM primitive on the BDF would link these elements of the hierarchy (BDF port through to the component in this hierarchy) but all it does is generate equivalent VHDL generics for the BDF, it does not 'wire through' these VHDL generics to the component in the BDF.
Has anyone else used VHDL generics in QuartusII (v9.0) and come this issue.
