Intel® Quartus® Prime Software
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Quartus FPGA error TCL Operation load notstatic

MinexTO
Beginner
532 Views

I'm downloading modelsim and using it on intel quartus lite, but I'm unable to do so when I do it, I get error saying TCL Operation Load Notstatic. I was able to run this properly before my pc was reset. 

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ShengN_Intel
Employee
334 Views

Hi,


Based on the error message:

Error: Top level entity/module name for test bench not specified -- cannot continue NativeLink simulation

Have you specify the correct testbench module name in Assignments->settings->EDA tool options->Simulation->Native Link Settings->testbenches?


Thanks,

Regards,

Sheng


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7 Replies
ShengN_Intel
Employee
498 Views

Hi,


May be try uninstall totally and reinstall using QuartusLiteSetup installer. Make sure also to set the Tool Executable path in Tools -> Options -> EDA Tool Options


Thanks,

Regards,

Sheng


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MinexTO
Beginner
438 Views

Hi,

I still have the same error ._.

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MinexTO
Beginner
416 Views

No, Also does the wun32olem appear automatically in the above method or we need to install separately (the modelsim)

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MinexTO
Beginner
413 Views
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
 
========= EDA Simulation Settings =====================
 
Sim Mode              :  RTL
Family                :  max10
Quartus root          :  c:/intelfpga_lite/23.1std/quartus/bin64/
Quartus sim root      :  c:/intelfpga_lite/23.1std/quartus/eda/sim_lib
Simulation Tool       :  questa intel fpga
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation\questa
 
=======================================================
 
Info: Starting NativeLink simulation with Questa Intel FPGA software
Sourced NativeLink script c:/intelfpga_lite/23.1std/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File Week2_run_msim_rtl_verilog.do already exists - backing up current file as Week2_run_msim_rtl_verilog.do.bak11
Error: Top level entity/module name for test bench not specified -- cannot continue NativeLink simulation
TCL OPERATION LOAD NOTSTATIC
Error: NativeLink simulation flow was NOT successful
 
 
 
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  NONE
Nativelink TCL script failed with errorInfo:  package "rdb21" isn't loaded statically
    while executing
"load "" rdb21 "
    invoked from within
"if [ catch {eval gen_msim_script args_hash} msim_do_file_name] {
error "$::errorCode" "$::errorInfo"
    } elseif {$script_mode == 0} {
post_message..."
    (procedure "launch_sim" line 112)
    invoked from within
"launch_sim launch_args_hash"
    ("eval" body line 1)
    invoked from within
"eval launch_sim launch_args_hash"
    invoked from within
"if [ info exists ::errorCode ] {
                set savedCode $::errorCode
                set savedInfo $::errorInfo
                error $result $..."
    invoked from within
"if [catch {eval launch_sim launch_args_hash} result ] {
            set status 1
            if [ info exists ::errorCode ] {
                set save..."
    (procedure "run_sim" line 74)
    invoked from within
"run_sim run_sim_args_hash"
    invoked from within
"if [ info exists ::errorCode ] {
            set savedCode $::errorCode
            set savedInfo $::errorInfo
            error "$result" $savedInfo ..."
    (procedure "run_eda_simulation_tool" line 334)
    invoked from within
"run_eda_simulation_tool eda_opts_hash"



from .rpt file
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ShengN_Intel
Employee
465 Views

Hi,


Do you have any further update or concern? Does your problem being resolved?


Thanks,

Regards,

Sheng


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ShengN_Intel
Employee
335 Views

Hi,


Based on the error message:

Error: Top level entity/module name for test bench not specified -- cannot continue NativeLink simulation

Have you specify the correct testbench module name in Assignments->settings->EDA tool options->Simulation->Native Link Settings->testbenches?


Thanks,

Regards,

Sheng


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MinexTO
Beginner
317 Views

Great,

I found the issue! It was exactly this, because of my silly mistake!

Thanks alot!

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