Quartus optimizing away my buffers

[Altera_Forum]

Hello, 

 Whenever I compile my project I recieve the warning(s):   Warning: Always-enabled tri-state buffer(s) removed Warning: Converted the fanout from the always-enabled tri-state buffer "Memory_Switch_Lite:inst8|TriState_Unidirectional_Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_component|dout[3]" to the node "MemoryOne_Clock" into a wire Warning: Converted the fanout from the always-enabled tri-state buffer "Memory_Switch_Lite:inst8|TriState_Unidirectional_Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_component|dout[1]" to the node "MemoryOne_WriteEnable" into a wire .... and so on.   These buffers are used to switch between two memory chips, the enables are connected to an input pin to allow them to be controlled from external circuitry, they may not change state on account of any of the logic that Quartus can see but they are not redundant!   Does anyone know how I can stop Quartus removing them?   I can't partition the design as I only have the free license, and I hear the precompiled library facility has been removed from Quartus II.   I've set the "remove redundant logic" to off in my compiler settings but still it persits.

[Altera_Forum]

can you check in the RTL viewer if the enable pin of the tri-state buffer is actually attached to an input pin? Quartus seems to think its tied to VCC.

[Altera_Forum]

Hi thepancake, 

 I have checked in RTL and it appears to be connected fine. I can see the input pin on all levels and its definately connected to the all the buffers 'enablet's.

[Altera_Forum]

Hi,  

 you can check the option "set flash bus pins to tri-state when not in use" on MegaWizard Plug-in Manager. I have the same warning message when using PFL and when i check the option, the warning message gone.  regards, konyemko

[Altera_Forum]

Hi konyemko, 

 Thanks for your reply!   Where abouts is that option? I can't see it anywhere in the plug-in manager for the buffers im using.   What is PFL? Perhaps it is specific to that component, ill have a look.

[Altera_Forum]

You can ignore the message. I'm guessing you're simply misunderstanding the meaning of the message. I don't have your design so I can't dissect it for you but it appears you've declared the signals: 

"Memory_Switch_Lite:inst8|TriState_Unidirectional_ Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_componen t|dout" "Memory_Switch_Lite:inst8|TriState_Unidirectional_ Buffer_24Bit:inst26|lpm_bustri:lpm_bustri_componen t|dout"   to be tri-state signals. Tri-state nodes do not exist in FPGAs (normally). They only exist at the IO pins. In other words, any tri-state signals used to drive internal FPGA logic will be converted to something (muxes, OR gates, wires, etc.) In your case, Quartus determined that these particular signals were always being driven from the specified locaiton and therefore simply turned them into wires.  If you want more details on the warning message, right-click on it in the report window and click "Help".  Jake

[Altera_Forum]

Hi Jake, 

 Thanks for your reply, it acctually does make more sense now that you've explained it like that, however im still concerned about one bit.   In your post you said "Quartus determined that these particular signals were always being driven from the specified locaiton and therefore simply turned them into wires."   My concern is that if it does indeed remove the internal muxes my design still won't work as intended.   The point of the buffers is to allow two sets of logic to drive the same output pins (which shall be connected to a memory chip), though obviously not at the same time. If you ask why I can't just disable the logic set while the other one is active, its because it will be writing to the Other memory chip.   In short, each logic set always tries to write to two sets of output pins, and the buffers are meant to block one or the other of these sets of signals.   I can see now though why Quartus may not 'understand' my circuit, since it has no concept of a high impedance state internally. I think I may have to redesign my switch with multiplexers explicitly.   Thanks!

[Altera_Forum]

Two suggestions: 

1 - Obviously I can't see your design but if you simulate your circuit, I think you'll see that it does work as you want it to.  2 - Read the section that begins on page 6-46 of the following document: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Generally, internal tri-states are a discouraged design practice.  Jake

[Altera_Forum]

Hi Jake, 

 My circuit does now appear to work as expected - before I was getting messages about logic contention, and I assumed because of the prior error message this was due to my lost buffers but ive taken a look at my VWF and there was a mistake with the simulated data from my 'memory'.   Thanks for the link! Ill have good read of that before doing anything else on this.