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Hi Everyone,
I am currently struggling with creating Active HDL macro with can accomplish the following.. 1) Create 'workspace' 2) Create 'project/design' with the workspace 3) Create and map libraries for designs/projects under the workspace 4) compile files 5) Compare I/O text files and report test results I plan to use these for an upcoming major verification task. I think steps 1 to 4 can be done via Altera's *.do macros', whereas I think I may have to use TCL or Perl for doing step 5. From another post, titled “Simulating with Aldec's Active-HDL and Riviera?" I did find a helpful script, which can assist me in doing steps 1-4, though I have yet to try it. Any help, useful links, tips would be much appreciated. Thanks :)Link Copied
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