Sending Array serially

[Altera_Forum]

Here's what I need to do, I have an array 16x16, and want to send one by one element to an output. 

I made an code, but when I put one line, the FPGA use wich was 10% becomes very higher and do not compile.  here's what I was doing:   TYPE array_t IS ARRAY (0 TO 15, 0 to 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0); output_a: OUT STD_LOGIC_VECTOR(7 downto 0); SIGNAL full_signal_output: array_t if rising_edge(clk_a) then if (all_done='0') then if (clk_var=256) then all_done<='1'; end if; if (clk_var<256) then clk_var<=clk_var+1; output_a <= full_signal_output(i, ii); ii<=ii+1; if (ii=15) then i<=i+1; ii<=0; end if; end if; end if; end if; ]  Any idea how can I do this?  Thank you.

[Altera_Forum]

A 16 x 16 x 8-bit array requires 2048-bits to implement. Your coding style likely causes the synthesizer to use logic elements to implement these bits. 

 If you are using an FPGA (not a MAX II CPLD), then the device has RAM blocks of varying sizes. One of those RAMs can be used to store your data, i.e., a 256 x 8-bit RAM block.  Read the handbook for the device you are using, and then use the MegaWizard to generate a RAM block.  Cheers, Dave

[Altera_Forum]

So you mean instead I use an signal to store my data, I should use a RAM, and the output I will read from the ram, right? 

 Actually this is a prototype, the real will be many more pixels. In a FPGA can have up to 270 Kbytes of ram?  I will search for the handbook. Thanks.

[Altera_Forum]

--- Quote Start ---  So you mean instead I use an signal to store my data, I should use a RAM, and the output I will read from the ram, right?   --- Quote End ---    Yes.    --- Quote Start ---   Actually this is a prototype, the real will be many more pixels. In a FPGA can have up to 270 Kbytes of ram?   --- Quote End ---    Some have this much. You can also add external RAM, eg., SRAM, DDR RAM, QDR RAM, etc. Look at several Altera evaluation boards and you will see examples of the various RAM types.   Cheers, Dave

[Altera_Forum]

Thank you dwh@ovro.caltech.edu!! (http://www.alteraforum.com/forum/member.php?u=21847) 

Actually I have never used memories. I am doing a project about image processing, an alternative version of DCT. I was thinking that would be possible import lets say 512x512(by 8 bits) to an "unprocessed" signal, process it all and save on a "processed" signal, but now I believe thats too much data.  The Kit I'll probably use (Arria II GX), have the memory needed. I will search about how to manipulate data into the memory.  Any tip about image processing would be very appreciated.  Thanks for all. 

[Altera_Forum]

Given you just mentioned you want a 512x512 array, it looks like you are trying to store an entire image.  

 The problem is, you are thinking like VHDL is software which has access to an entire 512x512 memory array. Its not like that in hardware. You can store the 512x512 array in a memory and read it out one pixel at a time. Using pipelining you can create a window into a small part of the image that you want to do the image processing on.  I do lots of image processing, and you never ever store the image in an array. I fear you havent got past thinking like a software programmer.

[Altera_Forum]

Thanks Tricky, i'll read about using memory. 

 But using the memory, I won't be able to simulate on ModelSim? I believe not, am I right?  Thank you.

[Altera_Forum]

there is no problem simulating memories in modelsim. You can either use megawizard altsyncrams or use infered memory. If its external ram, you can usually write a memory model.

[Altera_Forum]

Great. 

I'll start searching about using memories.  Thanks for all.

[Altera_Forum]

hi Tricky 

if u can write code for array 100x100 in external ram and using serialy , i'm using DE0

[Altera_Forum]

you didnt finish the sentence with what you'll pay me for doing your work.