Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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SignalTap, Nios and netlists

Altera_Forum
Honored Contributor II
1,052 Views

Hi, 

 

For the last two days I have been trying to set up SignalTap to extract the trace from a nios II processor. I have followed the AN446 application note, but when I compile I get the message "Partially connected in-system debug instance...". I have gathered from forum posts that the signals must be set as 'pre-synthesis' or 'source' type, but where?? As I am adding the Nios II nodes from a plugin it gives me no option, unlike when adding my own nodes. 

 

Also, incremental compilation must be disabled. I am using Quartus 11.0 and may be overlooking something, but I simply cannot find a 'disable' button, not even in the "Incremental Compilation" settings. 

 

I would very much appreciate any help! 

 

Josef
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Altera_Forum
Honored Contributor II
312 Views

I met the same problems with you !

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Altera_Forum
Honored Contributor II
312 Views

I have been asking around but no answer from anywhere :( Will let you know if I come across anything.

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Altera_Forum
Honored Contributor II
312 Views

A coworker of mine ran into this and I didn't have any good suggestions as workarounds. The Nios II signal tap II pluggin needs updating for this to work properly.

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Altera_Forum
Honored Contributor II
312 Views

Obviously I wasn't typing in the right keywords for within 10 seconds of reading the latest post I found a previous post on the same issue: 

 

http://www.alteraforum.com/forum/showthread.php?t=29483 

 

And indeed, by turning on "Create Debugging nodes for IP Corres" under Analysis & Synthesis->More Settings the whole thing suddenly works! Would have been nice if this had been written somewhere in the AN446 application note...
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Altera_Forum
Honored Contributor II
312 Views

Nice find, I didn't know about that option either.

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