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Hello all.
I am wondering if Quartus ii performs any state minimization, and if so, how is it used/enabled? Thank you- Tags:
- FPGA Design Tools
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Do you explicitly mean states, or logic?
State machines are encoded using one of several methods. Grey code, one hot and counter. By default it will encode 1 hot. Minimization can occur during synthesis- Mark as New
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--- Quote Start --- Do you explicitly mean states, or logic? State machines are encoded using one of several methods. Grey code, one hot and counter. By default it will encode 1 hot. Minimization can occur during synthesis --- Quote End --- I mean eliminating redundant states. Thank you very much for your time
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Assuming you mean states that cannot be entered, it might depend on the encoding scheme as to whether they are removed or not. The syntheses will remove any redundant logic.
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