Timequest results differ from Modelsim

[Altera_Forum]

So In Timequest I have a launch clock and a latch clock for some data. 

The latch clock is about a 0.2 ns delay after launch clock.    It modelsim using the slow model netlist, same as timequest, the delay between the same two clocks is 2.2 ns.   Now which one is correct? It is hard to know which way to swift the clock in the pll so it can meet timing especially since it is a 200 mhz and there is a 2ns difference between timequest and modelsim.   I have a tendency to trust Timequest over modelsim, because it is designed by Altera, and it knows what the launch and latch clock are.   But still why is there a difference? I am using gate level simulation, at least I think so. I am using Timquest after fitting the design.    Any ideas?

[Altera_Forum]

Your problem is not clear. The concept of latch/launch clock applies to one clock more often than it applies to two separate clocks. 

Any rtl chain clocked by one clock has lauch/latch at every register stage. So what do you mean then by "the" lauch clock and "the" latch clock?

[Altera_Forum]

I have a clock that drives an external ram. It's source is a port of the FPGA. I have another clock that clocks in the data. It's source is another pin of the pll. So they are two seperate clocks. 

 I am trying to figure out how to shift the second clock to get best results. But timequest and modelsim differ.

[Altera_Forum]

If I understood correctly, you have two clocks output by fpga with a a phase differnece set to .2 ns then modelsim shows 2.2 ns. 

I assume you can't actually measure quartus results but you have read the fitter report saying it achieved .2ns.  In that case you have an issue. One suggestion is that modelsim resolution must in ps for PLLs. I believe the default is ns. Try make it ps first.

[Altera_Forum]

Ok First there is one clock that is an output of the FPGA, This clock drives the ram, the ram then send data back to the FPGA, and then I use a second clock which is internal to the FPGA to clock in the data. 

 At the PLL, even though they are seperate outputs of the pll, The clocks currently have the same phase. I want to shift it to get better timing results.   In a SDC file i used a create_generated_clock command to create a clock on the output port of the FPGA. Then I constrained the I/O with set_input_delay min and max.... Then in Timequest I did a report_timing command on that ram data that is coming in. It has a launch clk = output clk. and a Latch clk = the pin of the pll. the difference between the two clocks is 0.2ns.   Then in modelsim, using the slow model netlist. I simulated the design. In the waveform I have the output clk, the output port of the FPGA, and i also have the pin of the PLL, or the internal clk. But the difference here is 2.2ns.    It just bugs me that modelsim has a different result.   how do you set resolution in modelsim. Can't you just set in the top testbench verilog file?   If I had the design on this computer i would do more copy and pasting and maybe do a screen capture, but the design computer doesn't have an internet connection for security reasons. but if you still need more information i can still copy the sdc and do some screen captures, it is just a hassle.

[Altera_Forum]

I think your observation is not right.  

In Modelsim you are right to see directly and compare but you are comparing output clock not with internal clock but with copy of internal clock as seen on the pin which implies uncertain delays. Moreover your timequest report dependancy for quartus is not right.  I suggest you ignore this issue. Instead get your timings right away from simulation. Frankly I never need to do gate level simulation but rather do functional rtl simulation and pass quartus timing.