Timing requirement not met.

[Altera_Forum]

Hi!  

 I'm new to FPGA. Recently, I compiled an licensed IP designed to be worked on Cyclone SOC V. The Quartus II I installed is 13.1 64-bit web edition for Linux. After the compilation done, there are quite a lot critical warnings in Timing Analysis.   timing requirement not met. timing was analysis was performed on core hps_sdram_p0 using quartus ii v13.1 with a prelimilary timing model and constraints. you must regenerate this ip in a future version of quartus ii to update the timing constraints to match the timing model.  I asked the licensor. He said he doesn't see these warnings on his Quartus II installation.  I tried to install the update 4 of Quartus II 13.1. The version shown on about dialog becomes 13.1.4 build 182. However, the same critical warnings are still there. Have anyone met this problem before? Any advises would be appreciated.

[Altera_Forum]

Without being an expert I would advice you to check on the Fitter settings. Perhaps the vendor's setup has different fitter settings causing his design to be fitted differently causing different timing. You could ask your vendor to provide you with his list of Fitter and/or Analysis&Synthesis settings.

[Altera_Forum]

Hi, 

 The answer is found in the Altera knowledge database: http://www.altera.com/support/kdb/solutions/rd03172014_960.html  It can be ignored, and is scheduled to be fixed in a future release.  Regards J

[Altera_Forum]

@pseudopajas, @polychronakis.o Thanks!