Trying to test Filter using NCO Megafunction and Signal Tap Analyzer?

[Altera_Forum]

I've built a low-pass filter using Fdatool in matlab and used HDL coder in matlab to get a vhdl to simulate on hardware. i'm trying to use the NCO megafunction to generate a signal to be filtered in the lowpass filter, and use a signal tap to get the results, but no matter what i try it doesn't seem to work. here are some screen shots i have attached of what i'm doing. 

 i'm not sure if i'm using the wrong triggers for the signal tap(They're set to don't cares), and i'm not sure if the clock i'm using is too fast (27 MHZ). Any help will be greatly appreciated.

[Altera_Forum]

I suspect its your trigger logic. You've got it setup to trigger when the NCO value is exactly all zeros. If you calculate how often that is likely to occur, you might find its infrequent. Try a different trigger source, eg. a push button, or Avalon-MM PIO signal. 

 Cheers, Dave

[Altera_Forum]

To determine, if the the NCO is outputting data, you don't need a trigger at all. Just acquire a few sampler in free running mode. 

 I can't see however, if the signals unconnected in your schematic blocks have suitable defaults.

[Altera_Forum]

--- Quote Start ---  I suspect its your trigger logic. You've got it setup to trigger when the NCO value is exactly all zeros. If you calculate how often that is likely to occur, you might find its infrequent. Try a different trigger source, eg. a push button, or Avalon-MM PIO signal.  Cheers, Dave  --- Quote End ---    I thought if i had all the triggers set to don't care, it wouldn't matter what change occurred at that particular node and the signal tap would activate.

[Altera_Forum]

--- Quote Start ---  I thought if i had all the triggers set to don't care, it wouldn't matter what change occurred at that particular node and the signal tap would activate.  --- Quote End ---    But you don't have them set to don't care, you have the first set to all zeros.  As FvM points out though, you can just start the capture, and then stop it manually, and you would see if data was changing.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  To determine, if the the NCO is outputting data, you don't need a trigger at all. Just acquire a few sampler in free running mode.   I can't see however, if the signals unconnected in your schematic blocks have suitable defaults.  --- Quote End ---     Can i please get more details on how to gather samples in free running mode? i'm not sure how to do that.

[Altera_Forum]

Testing a filter with NCO is of limited efficiency. A simple test is to inject impulse input i.e. first sample set high, others zero for some time and repeat this pattern. then you should get impulse response at output i.e. your coeffs scaled. 

The best way however is to pass random data to both your design and matlab "filter" function and check for bit true performance.

[Altera_Forum]

--- Quote Start ---  Testing a filter with NCO is of limited efficiency. A simple test is to inject impulse input i.e. first sample set high, others zero for some time and repeat this pattern. then you should get impulse response at output i.e. your coeffs scaled. The best way however is to pass random data to both your design and matlab "filter" function and check for bit true performance.  --- Quote End ---    Thanks Kaz...i'm getting a lot of great ideas from all poster, but i'm relatively new to Quartus II and testing through hardware. i need a more comprehensive approach to doing these idea. a guide or a link to a manual will be very helpful. for example how do i pass random data to the filter on FPGA. i do know how to use the "filter" function on matlab though, the thing is i need to test it on the FPGA.

[Altera_Forum]

You basically need to learn how to do a testbench. For your filter, the testbench itself is very simple if you know how to read text files.  

 You need to start from Matlab. Generate your random data and convert it to integers then into text file. pass your input to "filter" function using your fixed point coeffs and round up result into integers as per design then convert to text file (thus you have input file and output file).  Go to ModelSim, run your testench to read random data file and pass it to filter by assignment, read output file into your design and compare. There will be some delay depending on reset but you should get bit accurate result. If there is rounding error or scale issue then we can discuss that.  Note that you don't need to verify filter response in design as long as matlab can be used to study it. All you need is verify that your implementation matches that of matlab.  Normally you should use ModelSim before actual hardware testing. In hardware stage, you can design a synthesisable testbench e.g. putting your above input /output ref data in RAM then testing through a flag passed to led or signaltap. Or if you have software control you may read files from PC and capture to PC then compare in Matlab... lots of ways...

[Altera_Forum]

Hi Dansong, 

   --- Quote Start ---  i'm relatively new to Quartus II and testing through hardware. i need a more comprehensive approach to doing these idea. a guide or a link to a manual will be very helpful. for example how do i pass random data to the filter on FPGA. i do know how to use the "filter" function on matlab though, the thing is i need to test it on the FPGA.  --- Quote End ---  Here's some examples for you: http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip) http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)  It has testbenches, MATLAB code, LFSRs, etc.  Cheers, Dave

[Altera_Forum]

Thanks a ton Dwh. i'll read these documents and let you know my results.

[Altera_Forum]

Thanks Kaz...The matlab hdl coder automatically creates test benches for filter designs in vhdl. is there a way you can synthesis that, or do i still follow the way you suggested?

[Altera_Forum]

Hi, 

 I am not sure about your tool's features but I doubt it will generate synthesisable testbench which is rarely considered by design methodology as it wastes memory and is usually temporary.  Generally you can add to any project one test module consisting of one ram for stimulus input (fixed in mif or editable in memory editor) and another ram for reference output(again fixed in mif or editable) then you can use it to verify various modules within your project. The module will have a bit of logic to align and compare output with reference generating a flag. This is very useful if you don't have software to help you. Once project is signed off, you may remove the test module.

[Altera_Forum]

Okay thanks for your help guys finally got it working...but a few more questions. is the clock rate the same as the sampling rate?

[Altera_Forum]

clock is the actual physical clock you use to run your logic. sampling rate is the rate of a given data stream. 

 depending on your fortunes, the clock may be equal, less than or more than data rate. if clock is faster you may process more than one channel of data (if applicable). if your clock is lower you will need to split up your channel into say even/odd and process them accordingly, in this case there will be design dependency of even/odd...

[Altera_Forum]

Then how does one determine what the sampling frequency is, the whole time i was under the impression the clock rate was also the sampling rate. would the sample Depth in the signal tap analyzer be the sampling rate?

[Altera_Forum]

Sampling rate of your signal is inherent in that signal you are given for example it could be 27Msps then you are free to choose your system clock. The easiest way is to use a clock = 27MHz then you process each sample per clock.  

You may opt to use 54Mhz clock in which case you can process two channels(if you have two of them) of 27Msps; one channel per clock period sharing same one resource.   Additionally if you have one channel then you may process at double speed for resource sharing e.g. compute half of filter sum of products in one cycle and second half in second clock then add up both halves so you may use half multipliers.   If your clock is 13.5MHz then you need to double resource to process one channel into two subchannels (even/odd).   Normally if you have one data channel then there is no need to make your system clock any different from sampling rate unless you are short of resource.

[Altera_Forum]

One thing i forgot to mention actually was all though i had the clock set to 27Mhz, i actually used a 50MHz clock. The Cyclone 2 board i used only allows me to use that clock for signal tap analysis. so i wasnt really sure whether the clock rate was still 27Mhz or the 50Mhz i was actually using. hence why i was confused on what the sampling rate would be. i still am actually.:confused:

[Altera_Forum]

Let me put it this way. You want to filter your input signal, then what determines sample rate is the sample rate when that signal was or is converted in an ADC(originally, assuming no further up or down sampling is done) or it could be your signal is generated digitally (rather than ADC) i.e. playing an LUT in which case the sampling frequency is the clock frequency that reads LUT.

[Altera_Forum]

--- Quote Start ---  Let me put it this way. You want to filter your input signal, then what determines sample rate is the sample rate when that signal was or is converted in an ADC(originally, assuming no further up or down sampling is done) or it could be your signal is generated digitally (rather than ADC) i.e. playing an LUT in which case the sampling frequency is the clock frequency that reads LUT.  --- Quote End ---     No i'm still using NCO so the signal is generated digitally. The signal i have has a clock rate of 50Mhz, and a output frequency of 1Mhz. so does that mean it wud sample once every 50 clock cycles? i feel like the Multichannel explaination is too indepth and missing the point of my question.

[Altera_Forum]

Hi Dansong, 

   --- Quote Start ---  No i'm still using NCO so the signal is generated digitally. The signal i have has a clock rate of 50Mhz, and a output frequency of 1Mhz. so does that mean it wud sample once every 50 clock cycles? i feel like the Multichannel explaination is too indepth and missing the point of my question.  --- Quote End ---  A 1MHz sinusoid generated at 50MHz clock rate using an NCO generates a signal that is analogous to sampling a 1MHz sinusoid with a 50MHz ADC. In this example, your sample rate and clock rate are the same.  You could design a digital filter that also runs at 50MHz clock rate, and its construction would look like the 'classic' form you see in the documents I sent you.  If your 'system design' called for sampling a real-world signal that had content only out to 1MHz, then a 50MHz ADC would oversample the signal (since the Nyquist rate is 25MHz), allowing an analog filter with a slow rolloff to be used. The signal could then be digitally filtered to reduce the sample rate to say 50/20 = 2.5MHz, or mixed to complex-baseband and digitally filtered to between -1.25MHz and 1.25MHz.  Why do this? Well, your signal now has a 'sample rate' of either 5MHz real-valued samples, or 2.5MHz complex-valued samples, and your FPGA can operate at 50MHz, i.e., 20x or 40x faster. Now you have 20 or 40 FPGA clocks per sample, so you can re-use FPGA logic, eg., a single multiplier can be used to perform 20 or 40 operations before the next sample is ready.  Do you see how the 'sample rate' of the data and the 'clock rate' of the FPGA can be different? Once the data is inside the FPGA, its 'sample rate' depends on the signal processing operations you apply to the data.  Cheers, Dave