Using RAM for register

Altera_Forum · ‎03-27-2016

Hello everyone.

I'm testing the examples of “Embedded SoPC design...” by Pong P. Chu. In the code below Ineed the table to be located in RAM. After compilation the memory usage is zero. What did I do wrong?

Thanks.

Tool: Quartus II 13.0.1

Device: Cyclone II (EP2C5T144C6)

module adder (a, b, data, clk);
input  a, b;
output  data;
input clk;
reg  data_reg;
(* ramstyle = "M4K" *) reg  rom_data;
wire  addr;
always @(posedge clk)
  data_reg <= rom_data;
always @*
begin
  case (addr)
8'b00000000 : rom_data <= 4'b0000;
8'b00000001 : rom_data <= 4'b0001;
8'b00000010 : rom_data <= 4'b0010;
................................
8'b11111101 : rom_data <= 4'b1100;
8'b11111110 : rom_data <= 4'b1101;
 
  endcase
end  
 
assign data = data_reg; 
assign addr = {a, b};
  
endmodule

Altera_Forum · ‎03-27-2016

You didn't create a rom, you created an address decoder as the rom_data variable is only big enough for a single value. It needs to be an array of 256 values ask set on the init block, with the address selecting the correct value.


reg  rom_data 
Initial 
  foreach(rom_data) rom_data = i;
Always @(posedge clk) data <= rom_data;

Altera_Forum · ‎03-28-2016

Thank you for the answer. But why can't I use this technique? http://quartushelp.altera.com/15.0/mergedprojects/hdl/vlog/vlog_file_dir_romstyle.htm

Altera_Forum · ‎04-11-2016

There is the difference that the quartus design is clocked - yours is not. To go into a ram, you need an output data register.

Altera_Forum · ‎05-09-2016

I recommend you go to the template option in the Quartus mens (under edit I think) and look at the ROM and RAM templates, they show you exactly what to type and you can just click the insert button to have the RTL dropped in directly.