Using the cyclones internal clock as input for a circuit

[Altera_Forum]

Hey all, 

 I have a simple 3 bit counter designed in circus and set up my cyclone II to run the circuit. Right now hitting a button will increment the value by 1, but what I want to do is set up the circut so that the internal clock acts as input. Simply put, I want my counter to become a stopwatch. How would I go about using the Cyclone internal clock as input rather than a button? Thanks for any help!

[Altera_Forum]

Normally you don't use the clock itself as an input but rather a signal that is synchronized to the same clock. For example if there is a signal that you want to count how many clock cycles it was high for you would use the signal as a counter enable, and use the clock ... as a clock source. If you have a verilog or VHDL file open in Quartus you can go to the 'template' menu option and look that the example for a up counter with a count enable input to see what I mean. I'm sure if you search for "performance counter" you'll find other examples of the sort of thing I described.

[Altera_Forum]

By the way this section of the forum is for SoC FPGAs, I'll move the thread over to somewhere more appropriate.

[Altera_Forum]

Thanks for the reply BadOmen, 

 I'm not actually using VHDL or any languages, but rather block diagram files to design circuts. Would I need to do anything special to the assignment editor to allow the input to act like a clock and switch values?

[Altera_Forum]

I'm not sure how to respond since it's not really clear to me what you are trying to accomplish. A typical counter has a clock input which all synchronous operations (i.e. counting) operate on. You prevent the counter from incrementing by using a counter enable which enables the counter register to capture the new value which is the output + 1. If your existing logic doesn't have these I highly recommend structuring your counter around that since it'll make your life much easier. It might be worth looking at the "lpm_counter" megawizard function since it's structured around what a typical counter provides in terms of behavior and once you use something like that then performing time measurements becomes trivial. 

 From your desription it almost sounds like you were using the push button as the clock source previously. You do not want to do that in a FPGA design for various reasons, instead you should be using an actual periodic clock and register enables to enable/inhibit synchronous operations from occuring. I'm sure if you search around you'll find plenty of schematics of counters since I'm guessing plenty of schools have students doing this sort of thing.