Worst-Case Hold

[Altera_Forum]

Hi! 

In the process of learning TimeQuest Timing Analyzer,I found that there are so many intricate conceptions.such as "setup A","setup B","Hold check A1","Hold check A2".I spend a lot of time to comprehend that,but failed.   Is there anybody knows the "souce clock","destination clock" ,"setup A" and what the relationship between them?    thank you in advance!

[Altera_Forum]

--- Quote Start ---  Hi! In the process of learning TimeQuest Timing Analyzer,I found that there are so many intricate conceptions.such as "setup A","setup B","Hold check A1","Hold check A2".I spend a lot of time to comprehend that,but failed.   Is there anybody knows the "souce clock","destination clock" ,"setup A" and what the relationship between them?    thank you in advance!  --- Quote End ---    Hi,  before I go to your picture an explanation of the two timing parameters:  setup time  The length of time for which data that feeds a register via its data or enable input(s) must be present at an input pin before the clock signal that clocks the register is asserted at the clock pin.  hold time  The minimum length of time for which data that feeds a register via its data or enable input(s) must be retained at an input pin after the clock signal that clocks the register is asserted at the clock pin.  I assume that the rising edge of your source clock is the active edge, means the data will change after the rising edge.   Look to the first rising edge of the source clock. In front of this edge you have a rising edge of the destination clock. What needs to be check ? You have to check whether the source data is long enough stable ( Hold check A1). But that is not all to be checked regarding the first rising of the source clock. The next rising edge of the destination clock occurs before the next rising edge of the source clock. What needs to be checked ? You have to check whether the source data is long enough stable in front of the second rising edge of the destination clock (Setup A). When we go further in your diagramm the second  rising edge of the source code occurs. Again you have to check the hold time now for the second rising edge of the destination clock ( nearest rising edge of destination clock in front of the source clock) (Hold check A2). The next rissing edge of the source clock occurs before the rising edge of the destination clock, therefore an additional Hold check for the second rising edge of the destination clock is required ( Hold check B1) and so on ...  Kind regards  GPK

[Altera_Forum]

Thank you for your answer,but you can see that the source clock obviously faster than destination clock,which would lead to data lose in the practial desgin. 

Would you tell me the use of the timing?

[Altera_Forum]

--- Quote Start ---  Thank you for your answer,but you can see that the source clock obviously faster than destination clock,which would lead to data lose in the practial desgin. Would you tell me the use of the timing?  --- Quote End ---    Hi,  the clocks have a fix ratio of 10ns/8ns. That means you will have a finite number of phase relations of the clocks. That are excatly the four you see in the picture. After that the pattern starts again.  10 20 30 40 destination clock  8 16 24 32 40 source clock  After 40 ns the pattern starts again !  Kind regards  GPK

[Altera_Forum]

Do you means that the time differences between the lanch edge and latch edge is periodic?the time differences between the lanch edge and latch edge are different in a period 

 thank you!

[Altera_Forum]

--- Quote Start ---  Do you means that the time differences between the lanch edge and latch edge is periodic?the time differences between the lanch edge and latch edge are different in a period   thank you!  --- Quote End ---    Hi,  yes , all 40 ns the phase relations repeated !  Kind regards  GPK

[Altera_Forum]

which design would use this clock?would you give me an example? 

 I think this design is hard to implement,It's require the phase between the source clock and destination clock must be fixed.the relationship between the launch edge and latch edge would be changed alone with the phase's variation.   thank you!

[Altera_Forum]

--- Quote Start ---  which design would use this clock?would you give me an example?   I think this design is hard to implement,It's require the phase between the source clock and destination clock must be fixed.the relationship between the launch edge and latch edge would be changed alone with the phase's variation.   thank you!  --- Quote End ---    Hi,  no idea for a design at the moment. Maybe you should see it more as an example how  the timings are defined.   Kind regards  GPK

[Altera_Forum]

OK,Thank you all the same.